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EE105 Fall 2007Lecture 20, Slide 1Prof. Liu, UC Berkeley Lecture 20 OUTLINE Review of MOSFET Amplifiers MOSFET Cascode Stage MOSFET Current Mirror Reading: Chapter 9 ANNOUNCEMENTS HW#11 is due in 2 weeks, on 11/20. Review session: Fri. 11/9, 3-5PM in 306 Soda (HP Auditorium) Midterm #2 (Thursday 11/15 in Sibley Auditorium): Material of Lectures (HW# 7-10; Chapters 6,9,11) 4 pgs of notes (double-sided, 8.5”×11”), calculator allowed

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EE105 Fall 2007Lecture 20, Slide 2Prof. Liu, UC Berkeley Review: MOSFET Amplifier Design A MOSFET amplifier circuit should be designed to 1.ensure that the MOSFET operates in the saturation region, 2.allow the desired level of DC current to flow, and 3.couple to a small-signal input source and to an output “load”. Proper “DC biasing” is required! (DC analysis using large-signal MOSFET model) Key amplifier parameters: (AC analysis using small-signal MOSFET model) – Voltage gain A v v out /v in – Input resistance R in resistance seen between the input node and ground (with output terminal floating) – Output resistance R out resistance seen between the output node and ground (with input terminal grounded)

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EE105 Fall 2007Lecture 20, Slide 3Prof. Liu, UC Berkeley MOSFET Models The large-signal model is used to determine the DC operating point (V GS, V DS, I D ) of the MOSFET. The small-signal model is used to determine how the output responds to an input signal.

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EE105 Fall 2007Lecture 20, Slide 4Prof. Liu, UC Berkeley Comparison of Amplifier Topologies Common Source Large A v < 0 - degraded by R S Large R in –determined by biasing circuitry R out R D r o decreases A v & R out but impedance seen looking into the drain can be “boosted” by source degeneration Common Gate Large A v > 0 -degraded by R S Small R in - decreased by R S R out R D r o decreases A v & R out but impedance seen looking into the drain can be “boosted” by source degeneration Source Follower 0 < A v ≤ 1 Large R in –determined by biasing circuitry Small R out - decreased by R S r o decreases A v & R out

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EE105 Fall 2007Lecture 20, Slide 5Prof. Liu, UC Berkeley Common Source Stage

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EE105 Fall 2007Lecture 20, Slide 6Prof. Liu, UC Berkeley Common Gate Stage

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EE105 Fall 2007Lecture 20, Slide 7Prof. Liu, UC Berkeley Source Follower

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EE105 Fall 2007Lecture 20, Slide 8Prof. Liu, UC Berkeley CS Stage Example 1 M 1 is the amplifying device; M 2 and M 3 serve as the load. Equivalent circuit for small-signal analysis, showing resistances connected to the drain

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EE105 Fall 2007Lecture 20, Slide 9Prof. Liu, UC Berkeley CS Stage Example 2 M 1 is the amplifying device; M 3 serves as a source (degeneration) resistance; M 2 serves as the load. Equivalent circuit for small-signal analysis

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EE105 Fall 2007Lecture 20, Slide 10Prof. Liu, UC Berkeley CS Stage vs. CG Stage With the input signal applied at different locations, these circuits behave differently, although they are identical in other aspects. Common source amplifier Common gate amplifier

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EE105 Fall 2007Lecture 20, Slide 11Prof. Liu, UC Berkeley Composite Stage Example 1 By replacing M 1 and the current source with a Thevenin equivalent circuit, and recognizing the right side as a CG stage, the voltage gain can be easily obtained.

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EE105 Fall 2007Lecture 20, Slide 12Prof. Liu, UC Berkeley Composite Stage Example 2 This example shows that by probing different nodes in a circuit, different output signals can be obtained. V out1 is a result of M 1 acting as a source follower, whereas V out2 is a result of M 1 acting as a CS stage with degeneration.

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EE105 Fall 2007Lecture 20, Slide 13Prof. Liu, UC Berkeley NMOS Cascode Stage Unlike a BJT cascode, the output impedance is not limited by .

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EE105 Fall 2007Lecture 20, Slide 14Prof. Liu, UC Berkeley PMOS Cascode Stage

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EE105 Fall 2007Lecture 20, Slide 15Prof. Liu, UC Berkeley Short-Circuit Transconductance The short-circuit transconductance is a measure of the strength of a circuit in converting an input voltage signal into an output current signal: The voltage gain of a linear circuit is (R out is the output resistance of the circuit)

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EE105 Fall 2007Lecture 20, Slide 16Prof. Liu, UC Berkeley Transconductance Example

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EE105 Fall 2007Lecture 20, Slide 17Prof. Liu, UC Berkeley MOS Cascode Amplifier

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EE105 Fall 2007Lecture 20, Slide 18Prof. Liu, UC Berkeley PMOS Cascode Current Source as Load A large load impedance can be achieved by using a PMOS cascode current source.

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EE105 Fall 2007Lecture 20, Slide 19Prof. Liu, UC Berkeley MOS Current Mirror The motivation behind a current mirror is to duplicate a (scaled version of the) “golden current” to other locations. Current mirror conceptGeneration of required V GS Current Mirror Circuitry

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EE105 Fall 2007Lecture 20, Slide 20Prof. Liu, UC Berkeley MOS Current Mirror – NOT! This is not a current mirror, because the relationship between V X and I REF is not clearly defined. The only way to clearly define V X with I REF is to use a diode- connected MOS since it provides square-law I-V relationship.

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EE105 Fall 2007Lecture 20, Slide 21Prof. Liu, UC Berkeley Example: Current Scaling MOS current mirrors can be used to scale I REF up or down – I 1 = 0.2mA; I 2 = 0.5mA

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EE105 Fall 2007Lecture 20, Slide 22Prof. Liu, UC Berkeley Impact of Channel-Length Modulation

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EE105 Fall 2007Lecture 20, Slide 23Prof. Liu, UC Berkeley CMOS Current Mirror

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