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EE105 Fall 2007Lecture 21, Slide 1Prof. Liu, UC Berkeley Lecture 21 OUTLINE Frequency Response – Review of basic concepts – high-frequency MOSFET model – CS stage – CG stage – Source follower – Cascode stage Reading: Chapter 11 REMINDERS Review session: Fri. 11/9, 3-5PM in 306 Soda (HP Auditorium) Midterm #2 (Thursday 11/15, 3:30-5PM in Sibley Auditorium)

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EE105 Fall 2007Lecture 21, Slide 2Prof. Liu, UC Berkeley The impedance of C L decreases at high frequencies, so that it shunts some of the output current to ground. In general, if node j in the signal path has a small- signal resistance of R j to ground and a capacitance C j to ground, then it contributes a pole at frequency (R j C j ) -1 A v Roll-Off due to C L

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EE105 Fall 2007Lecture 21, Slide 3Prof. Liu, UC Berkeley Pole Identification Example 1

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EE105 Fall 2007Lecture 21, Slide 4Prof. Liu, UC Berkeley Pole Identification Example 2

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EE105 Fall 2007Lecture 21, Slide 5Prof. Liu, UC Berkeley Dealing with a Floating Capacitance Recall that a pole is computed by finding the resistance and capacitance between a node and (AC) GROUND. It is not straightforward to compute the pole due to C F in the circuit below, because neither of its terminals is grounded.

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EE105 Fall 2007Lecture 21, Slide 6Prof. Liu, UC Berkeley Miller’s Theorem If A v is the voltage gain from node 1 to 2, then a floating impedance Z F can be converted to two grounded impedances Z 1 and Z 2 :

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EE105 Fall 2007Lecture 21, Slide 7Prof. Liu, UC Berkeley Miller Multiplication Applying Miller’s theorem, we can convert a floating capacitance between the input and output nodes of an amplifier into two grounded capacitances. The capacitance at the input node is larger than the original floating capacitance.

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EE105 Fall 2007Lecture 21, Slide 8Prof. Liu, UC Berkeley Application of Miller’s Theorem

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EE105 Fall 2007Lecture 21, Slide 9Prof. Liu, UC Berkeley MOSFET Intrinsic Capacitances The MOSFET has intrinsic capacitances which affect its performance at high frequencies: 1.gate oxide capacitance between the gate and channel, 2.overlap and fringing capacitances between the gate and the source/drain regions, and 3.source-bulk & drain-bulk junction capacitances (C SB & C DB ).

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EE105 Fall 2007Lecture 21, Slide 10Prof. Liu, UC Berkeley High-Frequency MOSFET Model The gate oxide capacitance can be decomposed into a capacitance between the gate and the source (C 1 ) and a capacitance between the gate and the drain (C 2 ). – In saturation, C 1 (2/3)×C gate, and C 2 0. – C 1 in parallel with the source overlap/fringing capacitance C GS – C 2 in parallel with the drain overlap/fringing capacitance C GD

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EE105 Fall 2007Lecture 21, Slide 11Prof. Liu, UC Berkeley Example CS stage …with MOSFET capacitances explicitly shown Simplified circuit for high-frequency analysis

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EE105 Fall 2007Lecture 21, Slide 12Prof. Liu, UC Berkeley Transit Frequency The “transit” or “cut-off” frequency, f T, is a measure of the intrinsic speed of a transistor, and is defined as the frequency where the current gain falls to 1. Conceptual set-up to measure f T

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EE105 Fall 2007Lecture 21, Slide 13Prof. Liu, UC Berkeley Small-Signal Model for CS Stage

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EE105 Fall 2007Lecture 21, Slide 14Prof. Liu, UC Berkeley … Applying Miller’s Theorem Note that p,out > p,in

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EE105 Fall 2007Lecture 21, Slide 15Prof. Liu, UC Berkeley Direct Analysis of CS Stage Direct analysis yields slightly different pole locations and an extra zero:

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EE105 Fall 2007Lecture 21, Slide 16Prof. Liu, UC Berkeley I/O Impedances of CS Stage

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EE105 Fall 2007Lecture 21, Slide 17Prof. Liu, UC Berkeley CG Stage: Pole Frequencies CG stage with MOSFET capacitances shown

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EE105 Fall 2007Lecture 21, Slide 18Prof. Liu, UC Berkeley AC Analysis of Source Follower The transfer function of a source follower can be obtained by direct AC analysis, similarly as for the emitter follower (ref. Lecture 14, Slide 6)

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EE105 Fall 2007Lecture 21, Slide 19Prof. Liu, UC Berkeley Example

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EE105 Fall 2007Lecture 21, Slide 20Prof. Liu, UC Berkeley Source Follower: Input Capacitance Recall that the voltage gain of a source follower is Follower stage with MOSFET capacitances shown C XY can be decomposed into C X and C Y at the input and output nodes, respectively:

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EE105 Fall 2007Lecture 21, Slide 21Prof. Liu, UC Berkeley Example

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EE105 Fall 2007Lecture 21, Slide 22Prof. Liu, UC Berkeley Source Follower: Output Impedance The output impedance of a source follower can be obtained by direct AC analysis, similarly as for the emitter follower (ref. Lecture 14, Slide 9)

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EE105 Fall 2007Lecture 21, Slide 23Prof. Liu, UC Berkeley Source Follower as Active Inductor CASE 1: R G < 1/g m CASE 2: R G > 1/g m A follower is typically used to lower the driving impedance, i.e. R G is large compared to 1/g m, so that the “active inductor” characteristic on the right is usually observed.

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EE105 Fall 2007Lecture 21, Slide 24Prof. Liu, UC Berkeley Example

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EE105 Fall 2007Lecture 21, Slide 25Prof. Liu, UC Berkeley MOS Cascode Stage For a cascode stage, Miller multiplication is smaller than in the CS stage.

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EE105 Fall 2007Lecture 21, Slide 26Prof. Liu, UC Berkeley Cascode Stage: Pole Frequencies Cascode stage with MOSFET capacitances shown (Miller approximation applied)

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EE105 Fall 2007Lecture 21, Slide 27Prof. Liu, UC Berkeley Cascode Stage: I/O Impedances

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