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H. EvansRun IIb L1Cal Meeting: 6-Mar-031 Changes to the GAB Current System Architecture Changes to GAB to Streamline this Architecture How this Affects.

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Presentation on theme: "H. EvansRun IIb L1Cal Meeting: 6-Mar-031 Changes to the GAB Current System Architecture Changes to GAB to Streamline this Architecture How this Affects."— Presentation transcript:

1 H. EvansRun IIb L1Cal Meeting: 6-Mar-031 Changes to the GAB Current System Architecture Changes to GAB to Streamline this Architecture How this Affects the Schedule/Costs http://www.nevis.columbia.edu/~evans/l1cal/hardware/hardware.html H. EvansColumbia/Nevis

2 H. EvansRun IIb L1Cal Meeting: 6-Mar-032 Current TAB/GAB Architecture TAB I/O is Fierce Lots of Traces on Board –11 768-pin FPGAs +… No room for: –standard VME –SCL mezzanine GAB (currently) Deals w/ This 1.Trigger Functions 2.VME Interface 3.SCL Interface SignalI/OCablesWhere PowerIBusRear ADF TTsI30Rear Cal-TrackO3Front L2/L3O1Front Timing (SCL)I1Front VMEI/O1Front

3 H. EvansRun IIb L1Cal Meeting: 6-Mar-033 VME & SCL to the TAB Serial VME Interface LVDS protocol & same cable/connector type as ADF-to-TAB transmission Run at 15 MHz –download FPGAs~10s –TAB monitoring~10ms Serial SCL Interface LVDS & ADF-to-TAB cable Run at 7.6 MHz Reconstruct BX & TURN on TAB Local Clock for testing w/out SCL PairDescriptionPairDescription ser_clklink clockclk77.6 MHz clock ser_frm_in1 st bit marker + Addr(23:16)initinit request ser_addr_inAddr(15:0)turnSCL first_period ser_data_inInput Data(15:0)l1_acceptL1 Accept signal ser_frm_out1 st bit markerpulseinternal synchronization ser_data_outOutput Data(15:0)spare

4 H. EvansRun IIb L1Cal Meeting: 6-Mar-034 Testing the TAB Prototype Goal: have TAB ready for July Integration Problem: TAB Layout Difficult –Layout Tool (pads) barely up to the Task TAB Testing Stages at Nevis 1.Electrical/FPGA testsSignal Tap 2.Test Data ReadbackVME 3.Test Data w/ Simple TimingFake SCL 4.Output to GABGAB Full GAB Functionality not Required until Late in the Game Solution: Split GAB into Three Boards 1.VME Interfacevery simple, 6U? 2.SCL Interfacesimple, 6U? 3.GABlives in TAB crate, similar interfaces

5 H. EvansRun IIb L1Cal Meeting: 6-Mar-035 The New System Advantages TAB  July Integr. Test –comp’s necessary for TAB tests avail. when needed –impossible w/out changes Simplifies Design –GAB Layout easier –GAB testing easier –Maintenance easier Disadvantages Cost ? –orig: proto=$12K; prod=$8K –additional cost ~$4K (fab) Maybe this is an Advantage ? –Engineering ~same –Comp’s ~same as orig. est. –Fabrication signif. easier –6U vme + 9U shell vs 9U vme

6 H. EvansRun IIb L1Cal Meeting: 6-Mar-036 Prototype Schedule ItemOld SchedNew Sched TAB Assembled3/14/034/25/03 TAB Bench Tested5/16/036/30/03 GAB Assembled4/11/036/24/03 GAB Bench Tested7/15/038/29/03 VME Interface Assembled  4/18/03 VME Interface Tested  6/30/03 SCL Interface Assembled  5/2/03 SCL Interface Tested  6/30/03 Start Integration Test7/16/03 End Integration Test10/8/03 Production Schedule Unaffected

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