RPC Electronics Status Overall system TDC –Digitizing frequency issue (determine the bin size of the TDC value) Discriminator test result Trigger module.
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Presentation on theme: "RPC Electronics Status Overall system TDC –Digitizing frequency issue (determine the bin size of the TDC value) Discriminator test result Trigger module."— Presentation transcript:
RPC Electronics Status Overall system TDC –Digitizing frequency issue (determine the bin size of the TDC value) Discriminator test result Trigger module status Fabrication
Altera Cyclone II FPGA Altera Cyclone II FPGA 20X4rows connectors 32 channel (Timing bin = 106ns/64) Data 32 bits L1 trigger RPC(HBD) crate/BUS structure 6Ux160 mm VME size TDCTDC TDCTDC Output To L1 Clock fanout L1 primitives L1 GTM Slow Control 8/6 TDCs TDC Output To DCM Disc. 16 channels cable input 16 channels cable input 16 channels cable input 16 channels cable input On chamber Clock Master Serial download Serial download
Signal flow Temporary programming jig power LVDS discriminator output CMS RPC discriminator chip RPC Discriminator board RPC TDC board DCM data L1 data Cable adapter board
TDC digitizing frequency issue The FPGA uses 4x beam clock to generating the digitizing frequency. This frequency drive a counter. Discriminator pulse stop the counter. => TDC value Original idea is have use both edges of 320 MHz, 8*40 MHz, as TDC counter clock. One set per channel. 32 channel per chip –The circuit associate with positive and negative edges of the clock are routed as independent circuits. The circuits associate with the positive and negative clock edges has slightly different delay than ½ clock cycle. The two counters need to be aligned within 1.65ns to be useful. Otherwise one can not aligned the counters between positive and negative edge. As an backup solution, we use 44* beam clock frequency as the clock for TDC counter, 2.5ns time bin with 9.6MHz RHIC clock. –This is still better than we claim in the CDR, i.e. 3.3ns. In the mean time, we will still try to improve the 320 MHz compiling result.
The TDC Internal Test Pulse Scan test pulse step average TDC valueSigma on the TDC
Discriminator test One can inject test pulse into the CMS discriminator chip. –The test pulse couple into the input through ~1.2pf capacitor. The negative edge of the pulse need to come first. – This can be used to verify the cable or channel alive test. It is not mean to be used as calibration of the discriminator chips. One can also inject pulse into the front end. –Threshold effect study. –Input pulse height scan. (to be done) Test run for the Old and new chips. Check for the 10m cables drives
Test pulse setting 0xc0 ~ 8mv input 8 mv per step. Old chip Channel 26 Channel 32
Test pulse setting 0x60 ~ 4mv input 8 mv per step. (old chip) CMS Disc threshold Channel 26 Channel 28 Channel 32Channel 30 Channel 32 Threshold (8 mv per step) TDC TDC distribution at step =20 (160mv)
Test pulse setting 0x60 ~ 4mv input 8 mv per step. New chip ground tight Channel 26 Channel 28 Channel 26 Channel 32
Test pulse setting 0x60 ~ 4mv input 8 mv per step. New chip ground disconnected.
Discriminator Test pulse input vs. discriminator threshold. 4 mv per step. Old board step TDC Channel 12 TDC distribution, DAC step =80
Test pulse input vs. discriminator threshold. 4 mv per step. New chip, Analog/digital ground separated. Channel 14 TDC distribution, DAC step =80 TDC step
Test pulse input vs. discriminator threshold. 4 mv per step. New chip, DC/AC ground jumper connected Channel 14 TDC distribution, DAC step =80 Chnl=14 TDC step
DISC LVDS output at discriminator board DISC output after ~10 meter cables 69 ns time difference 1.61ns/ft ~42 ft Digitally subtracted pulse between + and – side of discriminator LVDS output 500mv per division 1.4V 1.63V
Trigger Module We have start to work on the trigger module FPGA code. –We will start with the design base on the the possibility the strips will be connected at the detector, i.e. the FEM will output 64 trigger bits per beam clock. –There is no TDC module changes to accommodate this changes. It will take us probably till late August/early September to finish all the coding and layout the board. There is no budget to fabricate this board. –Fund are re-allocated to the purchase of the parts for the factory setup and coming run.
Fabrication Status We are starting to assemble the discriminator modules in house with the final cable connectors, >12 finished. We have the clock master, clock fanout, TDC boards and parts. –Waiting for the purchase order for the assembly. For backplane, we are waiting for the purchase order for the boards. We need to work on the data taking software…