1. JTAG course - Dolev Eyal 1 JTAG environment Full Chip testing

2. JTAG course - Dolev Eyal 2 Test Logic Architecture  In the following presentation we will discuss the needs and means for the creation of a JTAG dft environment. –Within the chip –Outside of the chip  The environment is designed for: –RTL block testing –Creating the patterns for the testers –Gate-level testing –FPGA testing –Silicon testing

3. JTAG course - Dolev Eyal 3 Test Logic Architecture  Basically making a complicated testing seem so simple from the outside

4. JTAG course - Dolev Eyal 4 Test Logic Architecture  The following elements shall compose the test logic architecture within the chip: –A TAP –A TAP controller –An instruction register –A group of test data registers

5. JTAG course - Dolev Eyal 5 Test Access Port - TAP  The TAP is a general-purpose port that can provide access to many test support functions built into a component.  It is composed as a minimum of the three input connections and one output connection.  An optional fourth input connection provides for asynchronous initialization.

6. JTAG course - Dolev Eyal 6 TAP connections  Test clock input (TCK) –Provides the clock for the test logic. –Stored-state devices in the test logic shall retain their state indefinitely when the signal applied to TCK is stopped at 0.  Test mode select input (TMS) –This signal is decoded to the TAP controller to control test operations. –Shall be sampled on the rising edge of TCK.  Test data input (TDI) –Serial test instruction and data. –Shall be sampled on the rising edge of TCK.

7. JTAG course - Dolev Eyal 7 TAP connections continue…  Test data out (TDO) –Serial output for test instruction and data. –Changes in the state of the signal driven through TDO shall occur only on the falling edge of TCK.  Test reset input (TRST*) –Provides for asynchronous initialization of the TAP controller. –Active low.

8. JTAG course - Dolev Eyal 8 Interconnection of components compatible with the standard  The figures on the next slide illustrate three alternative board-level interconnections of components conforming to IEEE Std 1149.1- 2001 standard.

9. JTAG course - Dolev Eyal 9 Interconnection of components compatible with the standard Serial connection using one TMS signal Connection in two paralleled serial chains Multiple independent paths with common TMS and TCK signals

10. JTAG course - Dolev Eyal 10 Test Logic Architecture Top level design - figures Clock and/or controls A conceptual schematic of test logic

11. JTAG course - Dolev Eyal 11 Test Logic Architecture  The following elements shall be contained in the test logic architecture within the chip : –A TAP –A TAP controller –An instruction register –A group of test data registers

12. JTAG course - Dolev Eyal 12 The full chip - Communication chip example

13. JTAG course - Dolev Eyal 13 TAP Functional Overview  Compiles with the IEEE Std 1149.1 (“JTAG”) test architecture standard  additionally provides access to most of the full chip testability features  provides not only a customer-visible feature of the chip but also provides crucial proprietary functionality for silicon debug and production testing

14. JTAG course - Dolev Eyal 14 Inside the Chip JTAG FSM  The JTAG commands are 6 bit words chosen according to the IEEE standard and the test you want the JTAG to cover. For example:  The controller must implement the IEEE standard FSM. For example:  Using the JTAG commands we issue instructions to the correct test/action we want to activate. –BS,BIST,DAT and so on…

15. JTAG course - Dolev Eyal 15 The TAP controller The TAP state machine

16. JTAG course - Dolev Eyal 16 The TAP controller   The TAP controller is a synchronous finite state machine that responds to changes at the TMS and TCK signals of the TAP and controls the sequence of operations of the circuitry. The TAP state machine

17. JTAG course - Dolev Eyal 17 The TAP controller  All state transitions of the TAP controller shall occur based on the value of TMS at the time of a rising edge of TCK.  Actions of the test logic (instruction register, test data registers, etc.) shall occur on either the rising or the falling edge of TCK in each controller state. The TAP state machine

18. JTAG course - Dolev Eyal 18 The TAP state machine  Contains –Reset state –Run-test/idle state –Two major branches –Access to the TAP instruction register –Access to one of the TAP/core data registers  TMS pin is used as the controlling input. The TAP state machine

19. JTAG course - Dolev Eyal 19 The TAP state machine  Test-Logic-Reset –Test logic disabled –Normal operation of the processor can continue. –Enters this state: –When the TMS input is held active for at least five clocks. –When TRST_N is pulled active. –Upon power-up.

20. JTAG course - Dolev Eyal 20 The TAP state machine  Run-Test/Idle –The idle state of the TAP controller. –The contents of all test data registers retain their previous values. –Self tests may run.  Shift-DR-Scan –Temporary controller state.  Shift-IR-Scan –Temporary controller state.

21. JTAG course - Dolev Eyal 21 The TAP state machine  Capture-IR –The shift register contained in the instruction register loads a fixed value. (two lsb are 01) –Test data registers selected by the current instruction retain their previous state. –The instruction does not change. IR branch

22. JTAG course - Dolev Eyal 22 The TAP state machine  Shift-IR –The shift register contained in the Instruction Register is connected between TDI and TDO and is shifted one stage toward its serial output on each rising edge of TCK. –The output arrives at TDO on the falling edge of TCK. –The current instruction does not change in this state. The TAP state machine IR branch

23. JTAG course - Dolev Eyal 23 The TAP state machine  Exit1-IR –a temporary state. –TMS held high – the controller enters Update-IR which terminates the scanning process. –The current instruction does not change in this state. The TAP state machine  Pause-IR –Allows shifting of the Instruction Register to be temporarily halted. –The current instruction does not change in this state. IR branch

24. JTAG course - Dolev Eyal 24 The TAP state machine  Exit2-IR –a temporary state. –TMS held high – the controller enters Update-IR which terminates the scanning process. –The current instruction does not change in this state. The TAP state machine IR branch

25. JTAG course - Dolev Eyal 25 The TAP state machine  Update-IR –The instruction which has been shifted into the Instruction Register is latched onto the parallel output of the Instruction Register on the falling edge of TCK. IR branch

26. JTAG course - Dolev Eyal 26 The TAP state machine  Capture-DR –Data may be parallel- loaded into test data registers selected by the current instruction (on the rising edge of TCK). –The current instruction does not change in this state. DR branch

27. JTAG course - Dolev Eyal 27 The TAP state machine  Shift-DR –The Data Register connected between TDI and TDO as a result of selection by the current instruction is shifted one stage toward its serial output on each rising edge of TCK. –The output arrives at TDO on the falling edge of TCK. –The parallel, latched output of the selected Data Register does not change while new data is being shifted in. The TAP state machine DR branch

28. JTAG course - Dolev Eyal 28 The TAP state machine  Exit1-DR –a temporary state. –TMS held high – the controller enters Update- DR which terminates the scanning process. –The current instruction does not change in this state. The TAP state machine  Pause-DR –Allows shifting of the Instruction Register to be temporarily halted. –The current instruction does not change in this state. DR branch

29. JTAG course - Dolev Eyal 29 The TAP state machine  Exit2-DR –a temporary state. –TMS held high – the controller enters Update- DR which terminates the scanning process. –The current instruction does not change in this state. The TAP state machine DR branch

30. JTAG course - Dolev Eyal 30 The TAP state machine  Update-DR –Data from the shift register path is loaded into the latched parallel outputs of the selected Data Register (if applicable) on the falling edge of TCK. –This (and Test-Logic- Reset) are the only controller states in which the latched paralleled outputs of a data register can change. DR branch

31. JTAG course - Dolev Eyal 31 Test logic operation Instruction scan Test-Logic-reset Run-Test/Idle Select-DR-Scan Select-IR-Scan Capture-IR Shift-IR Exit1-IR Pause-IR Exit2-IR Update-IR

32. JTAG course - Dolev Eyal 32 TAP registers  Allows an instruction to be shifted into the design.  The instruction is used to select the test to be performed or the test data register to be accessed or both. The instruction register

33. JTAG course - Dolev Eyal 33 TAP registers  This register consists of 6 bit shift register and the actual instruction register.  The parallel output of the TAP instruction register goes to the TAP instruction decoder. The instruction register Operation of the TAP Instruction register

34. JTAG course - Dolev Eyal 34 TAP registers  In Capture-IR, the shift register portion of the instruction register is loaded in parallel with the fixed value “NOP”.  In Shift-IR, the shift register portion of the instruction register forms a serial data path between TDI and TDO.  In Update-IR, the shift register contents are latched in parallel into the actual instruction register. The instruction register

35. JTAG course - Dolev Eyal 35 The chip Top  Every Chip has a Top layer which contains all it’s IO pins (functional and testing)  The IO pins change their functionality from one feature to another.  In order to test the full chip we wrap this top with our own new top – AV top. Where we can control the JTAG IO pins and check the other IO pins

36. JTAG course - Dolev Eyal 36 AV Top TCK TMS TDI TDO IO pins

37. JTAG course - Dolev Eyal 37 Chip external dft environment Chip_dft Jtag_stubdft_utilsdft_strapsdft_testsdft_signals basic dft operations: basic dft operations: Writing a JTAG command, reading the output … Writing a JTAG command, reading the output … Different utils needed Strap utils: powering up, z straps, clock bypassing … Connecting the signals threw Hw paths The tests!! Block/FC tests

38. JTAG course - Dolev Eyal 38 Creating the patterns  After testing and approving the validity of the design on RTL we create patterns of 1 & 0 for each pin in the proper time.  We use the patterns for the Gate level testing and the silicon debug. TDI: 800ns – 1 850ns – 1 870ns – 0 ….

39. JTAG course - Dolev Eyal 39 Testing the Gate level & silicon  Using the JTAG device along with the patterns as inputs for the 4 (or 5) access ports for before and after silicon validation.

40. JTAG course - Dolev Eyal 40 Questions??

41. JTAG course - Dolev Eyal 41 Example of JTAG commands

42. JTAG course - Dolev Eyal 42 Write_to_ir -- going to shift_ir DRIVE tms 0; wait [1]; start latch_do(length,FALSE); -- write ir value for i from 0 to length-1 do { DRIVE tms i == (length-1) ? 1 : 0; DRIVE tdi value[i:i]; wait [1]; }; -- going to update_ir DRIVE tms 1; wait [1]; if (end_in_idle) { -- going to run-test-idle DRIVE tms 0; wait [1]; }else { -- going to select DR scan DRIVE tms 1; wait [1]; }; 'top.TB_JTAG_TCK_EN' = FALSE; }; write_to_ir(value : byte(bits:6),length : uint,start_from_idle : bool,end_in_idle : bool)@tck_free_clk_fall is { 'top.TB_JTAG_TCK_EN' = TRUE; if (start_from_idle) DRIVE tms 0; wait [1]; -- going to select DR scan DRIVE tms 1; wait [1]; -- going to select_ir DRIVE tms 1; wait [1]; -- going to capture_ir DRIVE tms 0; wait [1];

43. JTAG course - Dolev Eyal 43 // The state machine implementation (as 1149.1 spec Figure 5.1) // ---------------------------------------------------------------- wire taprst = ~i_jtag_trst_n || ~ior_i_lan_pwr_good; always @(posedge tapclk or posedge taprst) begin :tap_fsm_seq if (taprst) tapfsms_crnt_state[15:0] <= 16'b1000000000000000; else tapfsms_crnt_state[15:0] <= tapfsms_nxt_state[15:0]; end always @(i_jtag_tms or tapfsms_crnt_state) begin: tap_fsm_comb tapfsms_nxt_state[TAP_RESET] <= ( i_jtag_tms & tapfsms_crnt_state[TAP_RESET]) | ( i_jtag_tms & tapfsms_crnt_state[TAP_SELIR]) ; tapfsms_nxt_state[TAP_IDLE] <= (~i_jtag_tms & tapfsms_crnt_state[TAP_IDLE]) | (~i_jtag_tms & tapfsms_crnt_state[TAP_RESET]) | (~i_jtag_tms & tapfsms_crnt_state[TAP_UPDATEDR]) | (~i_jtag_tms & tapfsms_crnt_state[TAP_UPDATEIR]) ; tapfsms_nxt_state[TAP_SELDR] <= (i_jtag_tms & tapfsms_crnt_state[TAP_IDLE]) | (i_jtag_tms & tapfsms_crnt_state[TAP_UPDATEDR]) | (i_jtag_tms & tapfsms_crnt_state[TAP_UPDATEIR]) ; tapfsms_nxt_state[TAP_CAPDR] <= (~i_jtag_tms & tapfsms_crnt_state[TAP_SELDR]) ; tapfsms_nxt_state[TAP_SHIFTDR] <= (~i_jtag_tms & tapfsms_crnt_state[TAP_SHIFTDR]) | (~i_jtag_tms & tapfsms_crnt_state[TAP_CAPDR]) | (~i_jtag_tms & tapfsms_crnt_state[TAP_EXIT2DR]) ; tapfsms_nxt_state[TAP_EXIT1DR] <= ( i_jtag_tms & tapfsms_crnt_state[TAP_CAPDR]) | ( i_jtag_tms & tapfsms_crnt_state[TAP_SHIFTDR]) ; tapfsms_nxt_state[TAP_PAUSEDR] <= (~i_jtag_tms & tapfsms_crnt_state[TAP_PAUSEDR]) | (~i_jtag_tms & tapfsms_crnt_state[TAP_EXIT1DR]) ; tapfsms_nxt_state[TAP_EXIT2DR] <= (i_jtag_tms & tapfsms_crnt_state[TAP_PAUSEDR]) ; JTAG FSM

44. JTAG course - Dolev Eyal 44 tapfsms_nxt_state[TAP_UPDATEDR] <= (i_jtag_tms & tapfsms_crnt_state[TAP_EXIT1DR]) | (i_jtag_tms & tapfsms_crnt_state[TAP_EXIT2DR]) ; tapfsms_nxt_state[TAP_SELIR] <= ( i_jtag_tms & tapfsms_crnt_state[TAP_SELDR]) ; tapfsms_nxt_state[TAP_CAPIR] <= (~i_jtag_tms & tapfsms_crnt_state[TAP_SELIR]) ; tapfsms_nxt_state[TAP_SHIFTIR] <= (~i_jtag_tms & tapfsms_crnt_state[TAP_SHIFTIR]) | (~ i_jtag_tms & tapfsms_crnt_state[TAP_CAPIR]) | (~i_jtag_tms & tapfsms_crnt_state[TAP_EXIT2IR]) ; tapfsms_nxt_state[TAP_EXIT1IR] <= ( i_jtag_tms & tapfsms_crnt_state[TAP_CAPIR]) | ( i_jtag_tms & tapfsms_crnt_state[TAP_SHIFTIR]) ; tapfsms_nxt_state[TAP_PAUSEIR] <= (~i_jtag_tms & tapfsms_crnt_state[TAP_PAUSEIR]) | (~i_jtag_tms & tapfsms_crnt_state[TAP_EXIT1IR]) ; tapfsms_nxt_state[TAP_EXIT2IR] <= ( i_jtag_tms & tapfsms_crnt_state[TAP_PAUSEIR]) ; tapfsms_nxt_state[TAP_UPDATEIR] <= ( i_jtag_tms & tapfsms_crnt_state[TAP_EXIT1IR]) | ( i_jtag_tms & tapfsms_crnt_state[TAP_EXIT2IR]) ; end // block: tap_fsm_comb // The following lines are written as they are (and not as a single // assignement statement) on purpose. The way they are written will // cause hdlsyn to instantiate an asynchronously-resettable flop for // tapfsms_crnt_state, which is what is required by the 1149.1 spec. // Assign signals to their corresponding state wire tst_lgc_rst = tapfsms_crnt_state[TAP_RESET]; wire run_tst_idle = tapfsms_crnt_state[TAP_IDLE]; wire capture_dr = tapfsms_crnt_state[TAP_CAPDR]; wire shift_dr = tapfsms_crnt_state[TAP_SHIFTDR]; wire updt_dr = tapfsms_crnt_state[TAP_UPDATEDR]; wire capture_ir = tapfsms_crnt_state[TAP_CAPIR]; wire shift_ir = tapfsms_crnt_state[TAP_SHIFTIR]; wire update_ir = tapfsms_crnt_state[TAP_UPDATEIR]; always @(tapfsms_crnt_state) tap_trst_t <= tapfsms_crnt_state[TAP_RESET]; // tap_trst_t output when the state is TAP_RESET. JTAG FSM

45. JTAG course - Dolev Eyal 45 Connecting signals to HW path //// JTAG control //// verilog variable 'top.JTAG_TMS' using wire; verilog variable 'top.JTAG_TDI' using wire; verilog variable 'top.JTAG_TDO' using wire; verilog variable 'top.JTAG_TRST' using wire; //// initialize related //// verilog variable 'top.LAN_PWR_GOOD' using wire; verilog variable 'top.GIO_PWR_GOOD' using wire; verilog variable 'top.DEVICE_OFF_N' using wire; verilog variable 'top.MAIN_PWR_OK' using wire; //// normal strap related //// verilog variable 'top.POINTERS[8:0]' using wire; verilog variable 'top.TEST_MAC' using wire; example