1. S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 32: Array Subsystems (DRAM/ROM) Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley – Rabaey/Pearson]

2. S. Reda EN160 SP’07 Lecture outline Last time –Memory periphery (row/column circuitry) –Core cell: SRAM cells This time (different core cells) –DRAM cells –ROM cells –Non Volatile Read Write (NVRW) cells

3. S. Reda EN160 SP’07 3T DRAM cell XV dd -V t BL1 V dd WWL write RWLread BL2 V dd -V t VV  No constraints on device sizes (ratioless)  Reads are non-destructive  Value stored at node X when writing a “1” is V WWL - V tn M1 M2 M3 X BL1 BL2 WWL RWL CsCs

4. S. Reda EN160 SP’07 1T DRAM Cell M1 X BL WL CsCs C BL XV dd -V t WL write “1” BL V dd read “1” V dd /2 sensing Write: C s is charged (or discharged) by asserting WL and BL Read: Charge redistribution occurs between C BL and C s Read is destructive, so must refresh after read Leakage cause stored values to “disappear” → refresh periodically

5. S. Reda EN160 SP’07 The bit line is precharged to V DD /2

6. S. Reda EN160 SP’07 How DRAM cells are manufactured? Trench capacitor

7. S. Reda EN160 SP’07 DRAM subarray architectures sensitive to noise rejects common mode noise

8. S. Reda EN160 SP’07 ROMs Read-Only Memories are nonvolatile –Retain their contents when power is removed Mask-programmed ROMs use one transistor per bit –Presence or absence determines 1 or 0

9. S. Reda EN160 SP’07 NOR ROMs 4-word x 6-bit ROM –Represented with dot diagram –Dots indicate 1’s in ROM Word 0: 010101 Word 1: 011001 Word 2: 100101 Word 3: 101010 Looks like 6 4-input pseudo-nMOS NORs Dot diagram

10. S. Reda EN160 SP’07 NAND ROM All word lines high by default with exception of selected row No transistor with the selected word -> bitline pulled down Transistor with the selected word -> bitline remain high

11. S. Reda EN160 SP’07 Non Volatile Read/Write (NVRW) memories Floating gate Source Substrate Gate Drain n + n +_ p t ox t Device cross-section Schematic symbol G S D Same architecture as ROM structures A floating transistor gate is used similar to traditional MOS, except that an extra polysilicon strip is inserted between the gate and channel allow the threshold voltage to be progammable

12. S. Reda EN160 SP’07 Floating gate transistor programming 0 V - 5 V 0 V DS Removing programming voltage leaves charge trapped 5 V - 2.5 V 5 V DS Programming results in higherV T. 20 V 10 V5 V 20 V DS Avalanche injection Process is self-timing - Effectively increases Threshold voltage Floating gate is surrounded by an insulator material  traps the electrons

13. S. Reda EN160 SP’07 Flash Electrically Erasable ROMs Control gate erasure p-substrate Floating gate Thin tunneling oxide n 1 source n 1 drain programming To erase: ground the gate and apply a 12V at the source

14. S. Reda EN160 SP’07 Basic Operations in a NOR Flash Memory― Erase

15. S. Reda EN160 SP’07 Basic Operations in a NOR Flash Memory― Write

16. S. Reda EN160 SP’07 Basic Operations in a NOR Flash Memory― Read

17. S. Reda EN160 SP’07 Summary So far, we covered –Periphery ( row decoders / column circuitry) –For the memory core: SRAM cells DRAM cells ROM NVWRM