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© Digital Integrated Circuits 2nd Sequential Circuits Digital Integrated Circuits A Design Perspective Designing Sequential Logic Circuits.

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Presentation on theme: "© Digital Integrated Circuits 2nd Sequential Circuits Digital Integrated Circuits A Design Perspective Designing Sequential Logic Circuits."— Presentation transcript:

1 © Digital Integrated Circuits 2nd Sequential Circuits Digital Integrated Circuits A Design Perspective Designing Sequential Logic Circuits

2 © Digital Integrated Circuits 2nd Sequential Circuits Naming Conventions  In our text:  a latch is level sensitive  a register is edge-triggered  There are many different naming conventions  For instance, many books call edge- triggered elements flip-flops  This leads to confusion however

3 © Digital Integrated Circuits 2nd Sequential Circuits Latch versus Register  Latch stores data when clock is low D Clk Q D Q  Register stores data when clock rises Clk D D QQ

4 © Digital Integrated Circuits 2nd Sequential Circuits Latch-Based Design N latch is transparent when  = 0 P latch is transparent when  = 1 N Latch Logic P Latch 

5 © Digital Integrated Circuits 2nd Sequential Circuits Timing Definitions t CLK t D t c 2 q t hold t su t Q DATA STABLE DATA STABLE Register CLK DQ

6 © Digital Integrated Circuits 2nd Sequential Circuits Writing into a Static Latch D CLK D Converting into a MUX Forcing the state (can implement as NMOS-only) Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states

7 © Digital Integrated Circuits 2nd Sequential Circuits Mux-Based Latches Negative latch (transparent when CLK= 0) Positive latch (transparent when CLK= 1) CLK 1 0D Q 0 1D Q

8 © Digital Integrated Circuits 2nd Sequential Circuits Edge-Triggered Flip-flop

9 © Digital Integrated Circuits 2nd Sequential Circuits Static SR Flip-Flop Writing data by pure force No clock needed (Asynchronous) Clock version?

10 © Digital Integrated Circuits 2nd Sequential Circuits Registers for Pipelining

11 © Digital Integrated Circuits 2nd Sequential Circuits Registers for Pipelining Pipelined ?

12 © Digital Integrated Circuits 2nd Sequential Circuits SemiconductorMemories

13 © Digital Integrated Circuits 2nd Sequential Circuits Memory  Memory Classification  Memory Architectures  The Memory Core  Periphery

14 © Digital Integrated Circuits 2nd Sequential Circuits Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory EPROM E 2 PROM FLASH Random Access Non-Random Access SRAM DRAM Mask-Programmed Programmable (PROM) FIFO Shift Register CAM LIFO

15 © Digital Integrated Circuits 2nd Sequential Circuits Memory Timing: Definitions

16 © Digital Integrated Circuits 2nd Sequential Circuits Memory Architecture: Decoders Word 0 Word 1 Word 2 WordN 2 2 N 2 1 Storage cell M bitsM N words S 0 S 1 S 2 S N 2 2 A 0 A 1 A K 2 1 K 5 log 2 N S N 2 1 Word 0 Word 1 Word 2 WordN 2 2 N 2 1 Storage cell S 0 Input-Output (M bits) Intuitive architecture for N x M memory Too many select signals: N words == N select signals K = log 2 N Decoder reduces the number of select signals Input-Output (M bits) Decoder

17 © Digital Integrated Circuits 2nd Sequential Circuits Array-Structured Memory Architecture

18 © Digital Integrated Circuits 2nd Sequential Circuits Hierarchical Memory Architecture

19 © Digital Integrated Circuits 2nd Sequential Circuits Read-Only Memory Cells (ROM) WL BL WL BL 1 WL BL WL BL WL BL 0 V DD WL BL GND Diode ROMMOS ROM 1MOS ROM 2

20 © Digital Integrated Circuits 2nd Sequential Circuits MOS OR ROM WL[0] V DD BL[0] WL[1] WL[2] WL[3] V bias BL[1] Pull-down loads BL[2]BL[3] V DD

21 © Digital Integrated Circuits 2nd Sequential Circuits MOS NOR ROM WL[0] GND BL[0] WL[1] WL[2] WL[3] V DD BL[1] Pull-up devices BL[2]BL[3] GND

22 © Digital Integrated Circuits 2nd Sequential Circuits MOS NOR ROM Layout Programmming using the Active Layer Only Polysilicon Metal1 Diffusion Metal1 on Diffusion Cell (9.5 x 7 )

23 © Digital Integrated Circuits 2nd Sequential Circuits MOS NAND ROM All word lines high by default with exception of selected row WL[0] WL[1] WL[2] WL[3] V DD Pull-up devices BL[3]BL[2]BL[1]BL[0]

24 © Digital Integrated Circuits 2nd Sequential Circuits MOS NAND ROM Layout No contact to VDD or GND necessary; Loss in performance compared to NOR ROM drastically reduced cell size Polysilicon Diffusion Metal1 on Diffusion Cell (8 x 7 ) Programmming using the Metal-1 Layer Only

25 © Digital Integrated Circuits 2nd Sequential Circuits Precharged MOS NOR ROM PMOS precharge device can be made as large as necessary, but clock driver becomes harder to design. WL[0] GND BL[0] WL[1] WL[2] WL[3] V DD BL[1] Precharge devices BL[2]BL[3] GND pre f

26 © Digital Integrated Circuits 2nd Sequential Circuits Non-Volatile Memories The Floating-gate transistor (FAMOS) Floating gate Source Substrate Gate Drain n + n +_ p t ox t Device cross-section Schematic symbol G S D

27 © Digital Integrated Circuits 2nd Sequential Circuits Floating-Gate Transistor Programming 0 V 2 5 V 0 V DS Removing programming voltage leaves charge trapped 5 V 2 2.5 V 5 V DS Programming results in higherV T. 20 V 10 V5 V 20 V DS Avalanche injection

28 © Digital Integrated Circuits 2nd Sequential Circuits FLOTOX EEPROM Floating gate Source Substrate p Gate Drain n 1 n 1 FLOTOX transistor Fowler-Nordheim I-V characteristic 20–30 nm 10 nm -10 V 10 V I V GD

29 © Digital Integrated Circuits 2nd Sequential Circuits EEPROM Cell WL BL V DD Absolute threshold control is hard Unprogrammed transistor might be depletion  2 transistor cell

30 © Digital Integrated Circuits 2nd Sequential Circuits Flash EEPROM Control gate erasure p-substrate Floating gate Thin tunneling oxide n 1 source n 1 drain programming Many other options …

31 © Digital Integrated Circuits 2nd Sequential Circuits Cross-sections of NVM cells EPROMFlash Courtesy Intel

32 © Digital Integrated Circuits 2nd Sequential Circuits Characteristics of State-of-the-art NVM

33 © Digital Integrated Circuits 2nd Sequential Circuits Read-Write Memories (RAM)  STATIC (SRAM)  DYNAMIC (DRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended

34 © Digital Integrated Circuits 2nd Sequential Circuits 6-transistor CMOS SRAM Cell WL BL V DD M 5 M 6 M 4 M 1 M 2 M 3 BL Q Q

35 © Digital Integrated Circuits 2nd Sequential Circuits CMOS SRAM Analysis (Read) WL BL V DD M 5 M 6 M 4 M 1 V V V BL Q = 1 Q = 0 C bit C

36 © Digital Integrated Circuits 2nd Sequential Circuits CMOS SRAM Analysis (Write) BL = 1 = 0 Q = 0 Q = 1 M 1 M 4 M 5 M 6 V DD V WL

37 © Digital Integrated Circuits 2nd Sequential Circuits 6T-SRAM — Layout V DD GND Q Q WL BL M1 M3 M4M2 M5M6

38 © Digital Integrated Circuits 2nd Sequential Circuits Resistance-load SRAM Cell Static power dissipation -- Want R L large Bit lines precharged to V DD to address t p problem M 3 R L R L V DD WL QQ M 1 M 2 M 4 BL

39 © Digital Integrated Circuits 2nd Sequential Circuits SRAM Characteristics

40 © Digital Integrated Circuits 2nd Sequential Circuits 3-Transistor DRAM Cell No constraints on device ratios Reads are non-destructive Value stored at node X when writing a “1” = V WWL -V Tn WWL BL1 M 1 X M 3 M 2 C S 2 RWL V DD V 2 V T D V V 2 V T BL2 1 X RWL WWL

41 © Digital Integrated Circuits 2nd Sequential Circuits 3T-DRAM — Layout BL2BL1GND RWL WWL M3 M2 M1

42 © Digital Integrated Circuits 2nd Sequential Circuits 1-Transistor DRAM Cell

43 © Digital Integrated Circuits 2nd Sequential Circuits DRAM Cell Observations  1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out.  DRAM memory cells are single ended in contrast to SRAM cells.  The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation.  Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design.  When writing a “1” into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than V DD

44 © Digital Integrated Circuits 2nd Sequential Circuits Sense Amp Operation D V(1) V V(0) t V PRE V BL Sense amp activated Word line activated

45 © Digital Integrated Circuits 2nd Sequential Circuits 1-T DRAM Cell M 1 word line Diffused bit line Polysilicon gate Polysilicon plate Capacitor Cross-section Layout Metal word line Poly SiO 2 Field Oxide n + n + Inversion layer induced by plate bias Poly

46 © Digital Integrated Circuits 2nd Sequential Circuits Periphery  Decoders  Sense Amplifiers

47 © Digital Integrated Circuits 2nd Sequential Circuits Row Decoders Collection of 2 M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder

48 © Digital Integrated Circuits 2nd Sequential Circuits Hierarchical Decoders A 2 A 2 A 2 A 3 WL 0 A 2 A 3 A 2 A 3 A 2 A 3 A 3 A 3 A 0 A 0 A 0 A 1 A 0 A 1 A 0 A 1 A 0 A 1 A 1 A 1 1 Multi-stage implementation improves performance NAND decoder using 2-input pre-decoders

49 © Digital Integrated Circuits 2nd Sequential Circuits Dynamic Decoders Precharge devices V DD  GND WL 3 2 1 0 A 0 A 0 GND A 1 A 1  WL 3 A 0 A 0 A 1 A 1 2 1 0 V DD V V V 2-input NOR decoder 2-input NAND decoder

50 © Digital Integrated Circuits 2nd Sequential Circuits 4-input pass-transistor based column decoder Advantages: speed (t pd does not add to overall memory access time) Only one extra transistor in signal path Disadvantage: Large transistor count 2-input NOR decoder A 0 S 0 BL 0 1 2 3 A 1 S 1 S 2 S 3 D

51 © Digital Integrated Circuits 2nd Sequential Circuits 4-to-1 tree based column decoder Number of devices drastically reduced Delay increases quadratically with # of sections; prohibitive for large decoders buffers progressive sizing combination of tree and pass transistor approaches Solutions: BL 0 1 2 3 D A 0 A 0 A 1 A 1

52 © Digital Integrated Circuits 2nd Sequential Circuits Sense Amplifiers Idea: Use Sense Amplifer output input s.a. small transition

53 © Digital Integrated Circuits 2nd Sequential Circuits Differential Sense Amplifier Directly applicable to SRAMs M 4 M 1 M 5 M 3 M 2 V DD bit SE Out y

54 © Digital Integrated Circuits 2nd Sequential Circuits DRAM Timing


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