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Sistemi Elettronici Programmabili1 Progettazione di circuiti e sistemi VLSI Anno Accademico 2010-2011 Lezione 11 5.5.11 Memorie (vedi anche i file pcs1_memorie.pdf.

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Presentation on theme: "Sistemi Elettronici Programmabili1 Progettazione di circuiti e sistemi VLSI Anno Accademico 2010-2011 Lezione 11 5.5.11 Memorie (vedi anche i file pcs1_memorie.pdf."— Presentation transcript:

1 Sistemi Elettronici Programmabili1 Progettazione di circuiti e sistemi VLSI Anno Accademico 2010-2011 Lezione 11 5.5.11 Memorie (vedi anche i file pcs1_memorie.pdf pcs2_memorie.pdf – pcs3_memorie.pdf )

2 Sistemi Elettronici Programmabili2 Chapter Overview  Memory Classification  Memory Architectures  The Memory Core  Periphery  Reliability  Case Studies

3 Sistemi Elettronici Programmabili3 Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory EPROM E 2 PROM FLASH Random Access Non-Random Access SRAM DRAM Mask-Programmed Programmable (PROM) FIFO Shift Register CAM LIFO

4 Sistemi Elettronici Programmabili4 Memory Timing: Definitions

5 Sistemi Elettronici Programmabili5 Memory Architecture: Decoders Word 0 Word 1 Word 2 WordN - 2 N - 1 Storage cell M bitsM N words S 0 S 1 S 2 S N-2 A 0 A 1 A K K = log 2 N S N Word 0 Word 1 Word 2 WordN - 2 N1 Storage cell S 0 Input-Output (M bits) Intuitive architecture for N x M memory Too many select signals: N words == N select signals K = log 2 N Decoder reduces the number of select signals Input-Output (M bits) Decoder -

6 Sistemi Elettronici Programmabili6 Array-Structured Memory Architecture Problem: ASPECT RATIO or HEIGHT >> WIDTH Amplify swing to rail-to-rail amplitude Selects appropriate word - 2 L-K

7 Sistemi Elettronici Programmabili7 Contents-Addressable Memory Address Decoder I/O Buffers Commands 2 9 Validity Bits Priority Encoder Address Decoder I/O Buffers Commands 2 9 Validity Bits Priority Encoder Address Decoder Data (64 bits) I/O Buffers Comparand CAM Array 2 9 words3 64 bits Mask Control Logic R/W Address (9 bits) Commands 2 9 Validity Bits Priority Encoder

8 Sistemi Elettronici Programmabili8 Memory Timing: Approaches DRAM Timing Multiplexed Adressing SRAM Timing Self-timed

9 Sistemi Elettronici Programmabili9 Read-Only Memory Cells WL BL WL BL 1 WL BL WL BL WL BL 0 V DD WL BL GND Diode ROMMOS ROM 1MOS ROM 2

10 Sistemi Elettronici Programmabili10 MOS OR ROM WL[0] V DD BL[0] WL[1] WL[2] WL[3] V bias BL[1] Pull-down loads BL[2]BL[3] V DD

11 Sistemi Elettronici Programmabili11 MOS NOR ROM WL[0] GND BL[0] WL[1] WL[2] WL[3] V DD BL[1] Pull-up devices BL[2]BL[3] GND

12 Sistemi Elettronici Programmabili12 MOS NOR ROM Layout Programmming using the Active Layer Only Polysilicon Metal1 Diffusion Metal1 on Diffusion Cell (9.5 x 7 )

13 Sistemi Elettronici Programmabili13 MOS NAND ROM All word lines high by default with exception of selected row WL[0] WL[1] WL[2] WL[3] V DD Pull-up devices BL[3]BL[2]BL[1]BL[0]

14 Sistemi Elettronici Programmabili14 MOS NAND ROM Layout No contact to VDD or GND necessary; Loss in performance compared to NOR ROM drastically reduced cell size Polysilicon Diffusion Metal1 on Diffusion Cell (8 x 7 ) Programmming using the Metal-1 Layer Only

15 Sistemi Elettronici Programmabili15 Equivalent Transient Model for MOS NOR ROM Word line parasitics –Wire capacitance and gate capacitance –Wire resistance (polysilicon) Bit line parasitics –Resistance not dominant (metal) –Drain and Gate-Drain capacitance Model for NOR ROM V DD C bit r word c WL BL

16 Sistemi Elettronici Programmabili16 Equivalent Transient Model for MOS NAND ROM Word line parasitics –Similar to NOR ROM Bit line parasitics –Resistance of cascaded transistors dominates –Drain/Source and complete gate capacitance Model for NAND ROM V DD C L r word c c bit r WL BL

17 Sistemi Elettronici Programmabili17 Non-Volatile Memories The Floating-gate transistor (FAMOS) Floating gate Source Substrate Gate Drain n + n +_ p t ox t Device cross-section Schematic symbol G S D

18 Sistemi Elettronici Programmabili18 Floating-Gate Transistor Programming 0 V - 5 V 0 V DS Removing programming voltage leaves charge trapped 5 V -2.5 V 5 V DS Programming results in higherV T. 20 V 10 V5 V 20 V DS Avalanche injection

19 Sistemi Elettronici Programmabili19 A “Programmable-Threshold” Transistor

20 Sistemi Elettronici Programmabili20 FLOTOX EEPROM Floating gate Source Substrate p Gate Drain n 1 n 1 FLOTOX transistor Fowler-Nordheim I-V characteristic 20–30 nm 10 nm -10 V 10 V I V GD

21 Sistemi Elettronici Programmabili21 EEPROM Cell WL BL V DD Absolute threshold control is hard Unprogrammed transistor might be depletion  2 transistor cell

22 Sistemi Elettronici Programmabili22 Flash EEPROM Control gate erasure p-substrate Floating gate Thin tunneling oxide n 1 source n 1 drain programming Many other options …

23 Sistemi Elettronici Programmabili23 Basic Operations in a NOR Flash Memory: Erase

24 Sistemi Elettronici Programmabili24 Basic Operations in a NOR Flash Memory: Write

25 Sistemi Elettronici Programmabili25 Basic Operations in a NOR Flash Memory: Write

26 Sistemi Elettronici Programmabili26 Basic Operations in a NOR Flash Memory: Read

27 Sistemi Elettronici Programmabili27 NAND Flash Memory Unit Cell Word line(poly) Source line (Diff. Layer) Courtesy Toshiba

28 Sistemi Elettronici Programmabili28 NAND Flash Memory Word linesSelect transistor Bit line contactSource line contact Active area STI Courtesy Toshiba

29 Sistemi Elettronici Programmabili29 Characteristics of State-of-the-art NVM

30 Sistemi Elettronici Programmabili30 Read-Write Memories (RAM)  STATIC (SRAM)  DYNAMIC (DRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended

31 Sistemi Elettronici Programmabili31 6-transistor CMOS SRAM Cell WL BL V DD M 5 M 6 M 4 M 1 M 2 M 3 BL Q Q

32 Sistemi Elettronici Programmabili32 CMOS SRAM Analysis (Read) WL BL V DD M 5 M 6 M 4 M 1 V V V BL Q = 1 Q = 0 C bit C

33 Sistemi Elettronici Programmabili33 CMOS SRAM Analysis (Read) 0 0 0.2 0.4 0.6 0.8 1 1.2 0.5 Voltage rise [V] 11.21.52 Cell Ratio (CR) 2.53 Voltage Rise (V)

34 Sistemi Elettronici Programmabili34 CMOS SRAM Analysis (Write) BL = 1 = 0 Q = 0 Q = 1 M 1 M 4 M 5 M 6 V DD V WL

35 Sistemi Elettronici Programmabili35 CMOS SRAM Analysis (Write)

36 Sistemi Elettronici Programmabili36 Resistance-load SRAM Cell Static power dissipation -- Want R L large Bit lines precharged to V DD to address t p problem M 3 R L R L V DD WL QQ M 1 M 2 M 4 BL

37 Sistemi Elettronici Programmabili37 SRAM Characteristics

38 Sistemi Elettronici Programmabili38 3-Transistor DRAM Cell No constraints on device ratios Reads are non-destructive Value stored at node X when writing a “1” = V WWL -V Tn WWL BL1 M 1 X M 3 M 2 C S 2 RWL V DD V 2 V T D V V 2 V T BL2 1 X RWL WWL

39 Sistemi Elettronici Programmabili39 1-Transistor DRAM Cell Write: C S is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance Voltage swing is small; typically around 250 mV.  V BL V PRE –V BIT V PRE – C S C S C BL + ------------ == V

40 Sistemi Elettronici Programmabili40 DRAM Cell Observations  1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out.  DRAM memory cells are single ended in contrast to SRAM cells.  The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation.  Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design.  When writing a “1” into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than V DD

41 Sistemi Elettronici Programmabili41 1-T DRAM Cell Uses Polysilicon-Diffusion Capacitance Expensive in Area M 1 word line Diffused bit line Polysilicon gate Polysilicon plate Capacitor Cross-section Layout Metal word line Poly SiO 2 Field Oxide n + n + Inversion layer induced by plate bias Poly

42 Sistemi Elettronici Programmabili42 Static CAM Memory Cell

43 Sistemi Elettronici Programmabili43 CAM in Cache Memory Address Decoder Hit Logic CAM ARRAY Input Drivers TagHit Address SRAM ARRAY Sense Amps / Input Drivers DataR/W

44 Sistemi Elettronici Programmabili44 Periphery  Decoders  Sense Amplifiers  Input/Output Buffers  Control / Timing Circuitry

45 Sistemi Elettronici Programmabili45 Row Decoders Collection of 2 M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder

46 Sistemi Elettronici Programmabili46 Hierarchical Decoders A 2 A 2 A 2 A 3 WL 0 A 2 A 3 A 2 A 3 A 2 A 3 A 3 A 3 A 0 A 0 A 0 A 1 A 0 A 1 A 0 A 1 A 0 A 1 A 1 A 1 1 Multi-stage implementation improves performance NAND decoder using 2-input pre-decoders

47 Sistemi Elettronici Programmabili47 Dynamic Decoders Precharge devices V DD  GND WL 3 2 1 0 A 0 A 0 GND A 1 A 1  WL 3 A 0 A 0 A 1 A 1 2 1 0 V DD V V V 2-input NOR decoder 2-input NAND decoder

48 Sistemi Elettronici Programmabili48 Sense Amplifiers t p C  V  I av ----------------= make  V as small as possible smalllarge Idea: Use Sense Amplifer output input s.a. small transition

49 Sistemi Elettronici Programmabili49 Differential Sense Amplifier Directly applicable to SRAMs M 4 M 1 M 5 M 3 M 2 V DD bit SE Out y

50 Sistemi Elettronici Programmabili50 Differential Sensing ― SRAM

51 Sistemi Elettronici Programmabili51 Latch-Based Sense Amplifier (DRAM) Initialized in its meta-stable point with EQ Once adequate voltage gap created, sense amp enabled with SE Positive feedback quickly forces output to a stable operating point. EQ V DD BL SE

52 Sistemi Elettronici Programmabili52 Other Circuits for Memory Periphery Charge-based Amplifiers Single-to Differential Conversion Voltage Regulators Charge pumps and other solutions…

53 Sistemi Elettronici Programmabili53 Reliability and Yield

54 Sistemi Elettronici Programmabili54 Noise Sources in 1T DRam C cross electrode a -particles leakage C S WL BL substrate Adjacent BL C WBL

55 Sistemi Elettronici Programmabili55 Alpha-particles (or Neutrons) 1 Particle ~ 1 Million Carriers WL BL V DD n 1 a -particle SiO 2 1 1 1 1 1 1 2 2 2 2 2 2

56 Sistemi Elettronici Programmabili56 Yield Yield curves at different stages of process maturity (from [Veendrick92])

57 Sistemi Elettronici Programmabili57 Redundancy Memory Array Column Decoder Row Decoder Redundant rows Redundant columns Row Address Column Address Fuse Bank :

58 Sistemi Elettronici Programmabili58 Error-Correcting Codes Example: Hamming Codes with e.g. B3 Wrong 1 1 0 = 3

59 Sistemi Elettronici Programmabili59 Redundancy and Error Correction

60 Sistemi Elettronici Programmabili60 Trends in Memory Cell Area From [Itoh01]

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