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# S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 29: Datapath Subsystems 3/3 Prof. Sherief Reda Division of Engineering,

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S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 29: Datapath Subsystems 3/3 Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley – Rabaey/Pearson]

S. Reda EN160 SP’07 Outline Last two lectures –We talked about different kind of adders This lecture 1.Comparators 2.Shifters 3.Multipliers

S. Reda EN160 SP’07 Comparators 0’s detector:A = 00…000 1’s detector: A = 11…111 Equality comparator:A = B Magnitude comparator:A < B

S. Reda EN160 SP’07 1. 1’s and 0’s detectors 1’s detector: N-input AND gate 0’s detector: NOTs + 1’s detector (N-input NOR) When is this circuit structure a good idea?

S. Reda EN160 SP’07 1. Equality comparator Check if each bit is equal (XNOR, aka equality gate) 1’s detect on bitwise equality

S. Reda EN160 SP’07 1. Magnitude comparator  Compute B-A and look at sign  B-A = B + ~A + 1  For unsigned numbers, carry out is sign bit

S. Reda EN160 SP’07 2. Shifters Shifting a data word by a constant amount is trivial A programmable shifter is more complex Multibit shifter can be cascaded together

S. Reda EN160 SP’07 2. Barrel Shifter Signal passes through at most one transmission gate Total transistors = N 2 Dominated by wiring

S. Reda EN160 SP’07 2. Logarithmic shifter Total shift is decomposed into stages of 2 Speed of shifting N bits depends on log N Number of transistor = 2(log N)* N

S. Reda EN160 SP’07 Multipliers

S. Reda EN160 SP’07 Array multiplier Where is the critical path?

S. Reda EN160 SP’07 Critical path of MxN multiplier

S. Reda EN160 SP’07 Carry Save Multiplier The carry bits are not immediately added, but rather are “saved” for the next adder stage

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