1. 8/23-25/05ELEC5970-001/6970-001 Lecture 21 ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Power Consumption in a CMOS Circuit Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu

2. 8/23-25/05ELEC5970-001/6970-001 Lecture 22 Class Projects Study of leakage dynamic power in nanometer devices Low leakage technologies Charge recovery and adiabatic switching circuits Simulation-based power estimation tool Transistor-sizing for low power Logic and flip-flop design for low power Low power clock distribution Low power arithmetic circuits Low power memory design Benchmarking of low power microprocessors Low power system design

3. 8/23-25/05ELEC5970-001/6970-001 Lecture 23 Components of Power Dynamic –Signal transitions Logic activity Glitches –Short-circuit Static –Leakage P total =P dyn + P stat P tran + P sc + P stat

4. 8/23-25/05ELEC5970-001/6970-001 Lecture 24 Power of a Transition: P tran V DD Ground CLCL R on R=large v i (t) v o (t) i c (t)

5. 8/23-25/05ELEC5970-001/6970-001 Lecture 25 Charging of a Capacitor V C R i(t) v(t) Charge on capacitor, q(t)=C v(t) Current, i(t)=dq(t)/dt=C dv(t)/dt t = 0

6. 8/23-25/05ELEC5970-001/6970-001 Lecture 26 i(t)=C dv(t)/dt=[V – v(t)] /R dv(t)V – v(t) ───=───── dt RC dv(t) dt ∫ ─────=∫───── V – v(t) RC -t ln [V – v(t)]=──+ A RC Initial condition, t = 0, v(t) = 0 → A = ln V -t v(t)=V [1 – exp(───)] RC

7. 8/23-25/05ELEC5970-001/6970-001 Lecture 27 -t v(t)=V [1 – exp( ── )] RC dv(t) V -t i(t)=C ───=── exp( ── ) dt R RC

8. 8/23-25/05ELEC5970-001/6970-001 Lecture 28 Total Energy Per Charging Transition from Power Supply ∞∞ V 2 -t E trans =∫ V i(t) dt=∫ ── exp( ── ) dt 00 R RC =CV 2

9. 8/23-25/05ELEC5970-001/6970-001 Lecture 29 Energy Dissipated per Transition in Resistance ∞ V 2 ∞ -2t R ∫ i 2 (t) dt=R ── ∫ exp( ── ) dt 0 R 2 0 RC 1 = ─ CV 2 2

10. 8/23-25/05ELEC5970-001/6970-001 Lecture 210 Energy Stored in Charged Capacitor ∞ ∞ -t V -t ∫ v(t) i(t) dt= ∫ V [1-exp( ── )] ─ exp( ── ) dt 0 0 RC R RC 1 = ─ CV 2 2

11. 8/23-25/05ELEC5970-001/6970-001 Lecture 211 Transition Power Gate output rising transition –Energy dissipated in pMOS transistor = CV 2 /2 –Energy stored in capacitor = CV 2 /2 Gate output falling transition –Energy dissipated in nMOS transistor = CV 2 /2 Energy dissipated per transition = CV 2 /2 Power dissipation: P trans =E trans α f ck =α f ck CV 2 /2 α=activity factor

12. 8/23-25/05ELEC5970-001/6970-001 Lecture 212 Short Circuit Current, i sc (t) Time (ns) 0 1 Amp Volt V DD i sc (t) 0 V i (t) V o (t) V DD - V Tp V Tn tBtB tEtE I scmaxf

13. 8/23-25/05ELEC5970-001/6970-001 Lecture 213 Peak Short Circuit Current Increases with the size (or gain, β) of transistors Decreases with load capacitance, C L Largest when C L = 0 Reference: M. A. Ortega and J. Figueras, “Short Circuit Power Modeling in Submicron CMOS,” PATMOS’96, Aug. 1996, pp. 147-166.

14. 8/23-25/05ELEC5970-001/6970-001 Lecture 214 Short-Circuit Energy per Transition E scf = ∫ t B t E V DD i sc (t)dt = (t E – t B ) I scmaxf V DD /2 E scf = t f (V DD - |V Tp | -V Tn ) I scmaxf /2 E scr = t r (V DD - |V Tp | -V Tn ) I scmaxr /2 E scf = 0, when V DD = |V Tp | + V Tn

15. 8/23-25/05ELEC5970-001/6970-001 Lecture 215 Short-Circuit Energy Increases with rise and fall times of input Decreases for larger output load capacitance Decreases and eventually becomes zero when V DD is scaled down but the threshold voltages are not scaled down

16. 8/23-25/05ELEC5970-001/6970-001 Lecture 216 Short-Circuit Power Calculation Assume equal rise and fall times Model input-output capacitive coupling (Miller capacitance) Use a spice model for transistors –T. Sakurai and A. Newton, “Alpha-power Law MOSFET model and Its Application to a CMOS Inverter,” IEEE J. Solid State Circuits, vol. 25, April 1990, pp. 584-594.

17. 8/23-25/05ELEC5970-001/6970-001 Lecture 217 Short Circuit Power P sc =α f ck E sc

18. 8/23-25/05ELEC5970-001/6970-001 Lecture 218 P sc vs. C C (fF) Decreasing Input rise time 3ns 0% 45% 0.5ns P sc /P total 0.7μ CMOS 3575

19. 8/23-25/05ELEC5970-001/6970-001 Lecture 219 P sc, Rise Time and Capacitance V DD Ground CLCL R on R=large v i (t) v o (t) i c (t)+i sc (t) tftf trtr v o (t) ─── R↑

20. 8/23-25/05ELEC5970-001/6970-001 Lecture 220 i sc, Rise Time and Capacitance -t V DD [ 1- exp ( ───── )] v o (t) R↓ tf (t)C I sc (t) =──── =────────────── R↑ tf (t)

21. 8/23-25/05ELEC5970-001/6970-001 Lecture 221 i scmax, Rise Time and Capacitance Small C Large C tftf 1 ──── R↑ tf (t) i scmax v o (t) i t

22. 8/23-25/05ELEC5970-001/6970-001 Lecture 222 P sc, Rise Times, Capacitance For given input rise and fall times short circuit power decreases as output capacitance increases. Short circuit power increases with increase of input rise and fall times. Short circuit power is reduced if output rise and fall times are smaller than the input rise and fall times.

23. 8/23-25/05ELEC5970-001/6970-001 Lecture 223 Technology Scaling Scale down by factors of 2 and 4, i.e., model 0.7, 0.35 and 0.17 micron technologies Constant electric field assumed Capacitance scaled down by the technology scale down factor

24. 8/23-25/05ELEC5970-001/6970-001 Lecture 224 Bulk nMOSFET n+ p-type body (bulk) n+ L W SiO 2 Thickness = t ox Gate Source Drain Polysilicon

25. 8/23-25/05ELEC5970-001/6970-001 Lecture 225 Scaling Factor, α Constant electric field L = L / α W = W / α t ox = t ox / α V DD = V DD /α Capacitance → 1/α Gate delay → 1/α Area → 1/α 2 Power dissipation → 1/α 2 Power density constant Doping → α

26. 8/23-25/05ELEC5970-001/6970-001 Lecture 226 Technology Scaling Results Input t r or t f (ns) 1% 70% P sc /P total L=0.7μ, C=40fF 0.41.6 12% L=0.35μ, C=20fF L=0.17μ, C=10fF 60% 4% 16% 37%

27. 8/23-25/05ELEC5970-001/6970-001 Lecture 227 Effects of Scaling Down 1-16% short-circuit power at 0.7 micron 4-37% at 0.35 micron 12-60% at 0.17 micron Reference: S. R. Vemuru and N. Steinberg, “Short Circuit Power Dissipation Estimation for CMOS Logic Gates,” IEEE Trans. on Circuits and Systems I, vol. 41, Nov. 1994, pp. 762-765.

28. 8/23-25/05ELEC5970-001/6970-001 Lecture 228 Summary: Short-Circuit Power Short-circuit power is consumed by each transition (increases with input transition time). Reduction requires that gate output transition should not be faster than the input transition (faster gates can consume more short-circuit power). Increasing the output load capacitance reduces short-circuit power. Scaling down of supply voltage with respect to threshold voltages reduces short-circuit power.

29. 8/23-25/05ELEC5970-001/6970-001 Lecture 229 Components of Power Dynamic –Signal transitions Logic activity Glitches –Short-circuit Static –Leakage

30. 8/23-25/05ELEC5970-001/6970-001 Lecture 230 Leakage Power IGIG IDID I sub I PT I GIDL n+ Ground V DD R

31. 8/23-25/05ELEC5970-001/6970-001 Lecture 231 Leakage Current Components Subthreshold conduction, I sub Reverse bias pn junction conduction, I D Gate induced drain leakage, I GIDL due to tunneling at the gate-drain overlap Drain source punchthrough, I PT due to short channel and high drain-source voltage Gate tunneling, I G through thin oxide

32. 8/23-25/05ELEC5970-001/6970-001 Lecture 232 Subthreshold Current I sub = μ 0 C ox (W/L) V t 2 exp{(V GS -V TH )/nV t } μ 0 : carrier surface mobility C ox : gate oxide capacitance per unit area L: channel length W: gate width V t = kT/q: thermal voltage n: a technology parameter

33. 8/23-25/05ELEC5970-001/6970-001 Lecture 233 I DS for Short Channel Device I sub = μ 0 C ox (W/L) V t 2 exp{(V GS -V TH +ηV DS )/nV t } V DS = drain to source voltage η: a proportionality factor

34. 8/23-25/05ELEC5970-001/6970-001 Lecture 234 Increased Subthreshold Leakage 0V TH ’V TH Log I sub Gate voltage Scaled device IcIc

35. 8/23-25/05ELEC5970-001/6970-001 Lecture 235 Summary: Leakage Power Leakage power as a fraction of the total power increases as clock frequency drops. Turning supply off in unused parts can save power. For a gate it is a small fraction of the total power; it can be significant for very large circuits. Scaling down features requires lowering the threshold voltage, which increases leakage power; roughly doubles with each shrinking. Multiple-threshold devices are used to reduce leakage power.