1. Team M1 Enigma Machine Milestone 7 - 26 March, 2006 Design Manager: Prateek Goenka Adithya Attawar (M11) Shilpi Chakrabarti (M12) Mike Sokolsky (M14) Design Manager: Prateek Goenka

2. Status Finished: –Behavioral Verilog and C simulation –Structural Verilog –Logic optimization –Module-level spice delay and power simulations –Floorplan –Top-level schematic testing In Progress: –Functional block layout –Simulation of functional blocks To do: –Global Layout –Testing –Simulation STATUS

3. Layout done:Layout Needed: GatesROM Muxes and RegistersRAM DFF, TFF FlipflopsFSM Add_Mod263-bit and 5-bit serial input registers Wheel Counter CellsWheel Counter

4. Design Decisions Finalized the SRAM design Layout of Add_Mod26 Layout of 3-bit and 5-bit counter cells Updated layout of Wheel Counter Floorplan

5. Initial Floorplan

6. UPDATED FLOORPLAN

7. Schematic Delay: 68ps ExtractedRC Delay: 94ps Register

8. Schematic of Add_Mod26

9. LAYOUT OF ADD_MOD26

10. LOOKAHEAD MODULE LAYOUT

11. LOOKAHEAD 2 MODULE LAYOUT

12. SUBTRACTOR MODULE LAYOUT

13. 3-bit Comparator

14. 3-bit Counter Cell 3, 1-bit T Flips FlopsCount Logic

15. 3-bit Counter

16. 5-bit Counter Cell 5, 1-bit D/T Flips Flops Count Logic w/ Reset at 26

17. Wheel Counter Plan (Module layout and wire planning) 5-bit Counter Cell Data from counters Wheel Select Wheel Position 5-bit Counter Cell