1. Sprinkler Buddy Presentation #5: “Transistor Level Schematics and Another Floor Plan” 2/21/2007 Team M3 Sasidhar Uppuluri Kalyan Kommineni Kartik Murthy Panchalam Ramanujan Design Manager: Bowei Gai “Low Cost Irrigation Management For Everyone ! ”

2. Current Status Determine Project Develop Project Specifications Plan Architectural Design Determination of all components in design Detailed logical flowchart Design a Floor Plan (refined again) Create Structural Verilog Make Transistor Level Schematic (some control issues) Layout  Testing (Extraction, LVS, and Analog Sim.) 

3. Floor Plan Old (Naïve) Floor Plan

4. Somewhat Better Floor Plan

5. Last Week’s Floor Plan

6. This Week’s First Try

7. Current Floor Plan

8. Individual Modules: BlockMetal Layers That Can be Used 40:20 MuxesM1 & M2 60:20 MuxesM1 & M2 CountersM1 & M2 KC ROMM1 & M2 & M3 & M4 P ROMM1 & M2 & M3 & M4 Metric Storage SRAMSM1 & M2 & M3 & M4 Constant Storage ROMM1 & M2 & M3 & M4 Floating Point AddersM1 & M2 & M3 Floating Point MultipliersM1 & M2 & M3 & M4 10 Bit RegistersM1 & M2

9. Transistor Count … Block (# used)Old TCNew TC 40:20 Muxes (6)~480362 60:20 Muxes (2)~720644 Counter (2)~250220 KC ROM (1)~7781256 P ROM (1)~82122 Metric Storage SRAMS (2) ~25222430 Constant Storage ROM (1) ~202428 Floating Point Adder (4) ~30003210 Floating Point Multiplier (2) ~28001398 10 Bit Registers (9) ~140210 Datapath Logic / Misc. ~20002305 Total = 30,397

10. New Design Size Block (# used)Size Estimate (um) 40:20 Muxes (4)20 x 80 60:20 Muxes (2)20 x 120 Counter (2)12 x 17 KC ROM (4 parts)181 x 8 P ROM (1)70 x 8 Metric Storage SRAMS (2) 181 x 60 Constant Storage ROM (1) 181 x 8 Floating Point Adder (4) 100 x 100 Floating Point Multiplier (2) 95 x 125 10 Bit Registers (8)50 x 10 457um x 391 um ~ 1 : 1.16 aspect ratio.178 mm^2 area.168 Transistor Density

11. Schematics: SRAM

12. Schematics: Flip Flops

13. Schematics: Read & Write to SRAM Read Write

14. Schematics: ROMs

15. Schematics: FP Units Multiplier Adder

16. Schematics: Control Hourly Update FP Adder

17. Design Challenges and Implementation Decisions For The Past Week Design Challenge Translation to HW Low Power Design Logic Reduction Sizing of Gates According to Logical Effort

18. Problems/Questions Small Problems with Control Logic in Schematic Can we reduce more transistors with better logic ? Any way to move the SRAM from the middle of our chip?

19. For Next Week Perfect our Control Logic in the Schematic Continue to reduce and optimize gates Start Layout !

20. Some Other Slides For Reference…

21. Block Size Estimates Block (# used)Size Estimate (um) 40:20 Muxes (4)20 x 80 60:20 Muxes (2)20 x 120 Counter (2)12 x 17 KC ROM (4 parts)181 x 8 P ROM (1)70 x 8 Metric Storage SRAMS (2)181 x 60 Constant Storage ROM (1)181 x 8 Floating Point Adder (4)100 x 100 Floating Point Multiplier (2)95 x 125 10 Bit Registers (8)50 x 10