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09/06/2015T. Evartson1

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1 09/06/2015T. Evartson1 http://www.klabs.org/richcontent/fpga_content/pages/notes/fpga_asic_vendors.htm http://www.klabs.org/fpgas.htm http://www.fpga-guide.com/ http://www.interfacebus.com/Programmable_Logic.html http://www.soccentral.com/results.asp?CatID=180 http://www.fpga4fun.com/FPGAinfo1.html http://hackaday.com/2008/12/11/how-to-programmable-logic-devices-cpld/ http://www.digilentinc.com/

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6 09/06/2015T. Evartson6 LatticeECP4 LatticeECP3 LatticeECP2/M Lattice semiconductor FPGA http://www.latticesemi.com

7 09/06/2015T. Evartson7 Lattice

8 09/06/2015T. Evartson8 MachXO2, MachXO Lattice

9 09/06/2015T. Evartson9 MachXO2-1200 Konfiguratsiooni mälu

10 09/06/2015T. Evartson10 iCE40 Lattice

11 09/06/2015T. Evartson11 I²C (Inter-Integrated Circuit) Philipsi aegrane siin SPI (Serial Peripheral Interface) Motorola sync. järjestiksiin (dupleks) Lattice

12 09/06/2015T. Evartson12 Lattice semiconductor CPLD ispMACH 4000ZE

13 09/06/2015T. Evartson13 Actel IGLOO nanao, IGLOO PLUS (Flash) http://www.actel.com/

14 09/06/2015T. Evartson14 ProASIC3, ProASIC nano, ProASIC3L Actel

15 09/06/2015T. Evartson15 Axcelerator (Antifuse) Actel

16 09/06/2015T. Evartson16 Actel

17 09/06/2015T. Evartson17 SX-A Actel

18 09/06/2015T. Evartson18 Actel

19 09/06/2015T. Evartson19 Actel

20 09/06/2015T. Evartson20 eX Actel

21 09/06/2015T. Evartson21 MX Actel

22 09/06/2015T. Evartson22 Actel

23 09/06/2015T. Evartson23 Actel

24 09/06/2015T. Evartson24 Actel

25 09/06/2015T. Evartson25 Altera MAX V, MAX II http://www.altera.com/ ALTERA

26 09/06/2015T. Evartson26 Altera

27 09/06/2015T. Evartson27 Altera

28 09/06/2015T. Evartson28 Altera

29 09/06/2015T. Evartson29 Altera

30 09/06/2015T. Evartson30 MAX 3000 ALTERA

31 09/06/2015T. Evartson31 Altera

32 09/06/2015T. Evartson32 Stratix V ALTERA

33 09/06/2015T. Evartson33 Altera

34 09/06/2015T. Evartson34 Altera

35 09/06/2015T. Evartson35 Altera

36 09/06/2015T. Evartson36 Altera

37 09/06/2015T. Evartson37 Altera

38 09/06/2015T. Evartson38 Arria II ALTERA

39 09/06/2015T. Evartson39 Altera

40 09/06/2015T. Evartson40 ARM Cortex – A9 ALTERA

41 09/06/2015T. Evartson41 Altera

42 09/06/2015T. Evartson42 Altera

43 09/06/2015T. Evartson43 Cyclone V ALTERA

44 09/06/2015T. Evartson44 Altera

45 09/06/2015T. Evartson45 Quicklogic ArcticLinc http://www.quicklogic.com/ Quicklogic

46 09/06/2015T. Evartson46 PolarPro 3 Quicklogic

47 09/06/2015T. Evartson47 Quicklogic

48 09/06/2015T. Evartson48 Quicklogic

49 09/06/2015T. Evartson49 Quicklogic

50 09/06/2015T. Evartson50 FPGAs Enable Bill of Materials Cost Reduction & Power Savings XILINX AMS Access Method Services

51 09/06/2015T. Evartson51 XILINX

52 09/06/2015T. Evartson52 XILINX

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55 09/06/2015T. Evartson55 Xilinx CoolRunner XILINX www.xilinx.com

56 09/06/2015T. Evartson56 XC9500 http://www.xilinx.com/

57 09/06/2015T. Evartson57 XILINX

58 09/06/2015T. Evartson58 XILINX

59 09/06/2015T. Evartson59 XILINX

60 09/06/2015T. Evartson60 Spartan 3E XILINX

61 09/06/2015T. Evartson61 XILINX

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65 09/06/2015T. Evartson65 XILINX www.xilinx.com

66 09/06/2015T. Evartson66 7 seeria

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69 09/06/2015T. Evartson69 CLBs, Slices, and LUTs Some key features of the CLB architecture include: Real 6-input look-up tables (LUTs) Memory capability within the LUT Register and shift register functionality Clock Management Some of the key highlights of the clock management architecture include: High-speed buffers and routing for low-skew clock distribution Frequency synthesis and phase shifting Low-jitter clock generation and jitter filtering Each 7 series FPGA has up to 24 clock management tiles (CMTs), each consisting of one mixed-mode clock manager (MMCM) and one phase-locked loop (PLL)

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71 09/06/2015T. Evartson71 SPLD LATTICE Cypress ATMEL OP Semiconductor Texas Instruments E2v Diodes Incorporated Seitsmel tootjal 443 toodet


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