1. LabView FPGA Communication Bin, Ray HEP, Syracuse Bin, Ray HEP, Syracuse

3. SEU TEST –Use 32-bit counter generate data, –Serialize the data by PISO S.R., then shift the data through the chain of SISO S.R. –Deserialize the data to reconstruct to the result of the 32-bit counter. –Add 1 and store the data, then comparing with the next coming 32-bit data. –The differences between the two data is considered as the result of the SEU, and count the number of SEU. –Count the total number of data and calculate the SEU percentage. –Use 32-bit counter generate data, –Serialize the data by PISO S.R., then shift the data through the chain of SISO S.R. –Deserialize the data to reconstruct to the result of the 32-bit counter. –Add 1 and store the data, then comparing with the next coming 32-bit data. –The differences between the two data is considered as the result of the SEU, and count the number of SEU. –Count the total number of data and calculate the SEU percentage.

4. PISO Shift Register → Barrel Shifter In the document, it is said that “The LSB is loaded with Shiftin”. We also contacted with Actel, but no response… So we use barrel shifter instead of the PISO S.R. –We could use B.S. as the serializer, but it decreases the speed of test. –In the simulation, we meet another question. In the document, it is said that “The LSB is loaded with Shiftin”. We also contacted with Actel, but no response… So we use barrel shifter instead of the PISO S.R. –We could use B.S. as the serializer, but it decreases the speed of test. –In the simulation, we meet another question.

5. To remove the phase difference Counter, to generate 32-bit data B.S., to serialize the data

6. The peaks have different widths, such as 100ps and 200ps. Point to different directions The peaks have different widths, such as 100ps and 200ps. Point to different directions Data Result Result of subtractor

7. The result has the form by A7 A6 A5 A4 A3 A2 A1 A0 A5&A4 are controlling the power of the PLLs A2, A1&A0 are controlling the first multiplexer (different frequencies of the PLL) A7, A6&A3 are controlling the second multiplexer (choosing the final output to the LabView) A5&A4 are controlling the power of the PLLs A2, A1&A0 are controlling the first multiplexer (different frequencies of the PLL) A7, A6&A3 are controlling the second multiplexer (choosing the final output to the LabView) CMD(HEX)Subtrahend(H/B)Result(Binary)Meaning AA/1010 1010 A9/1010 1001 00 00 0001 Checking Status of FPGA B9/1011 100100 01 0000 Active 300MHz CLK BB/1011 101100 01 0010 Active 150MHz CLK BC/1011 110000 01 0011 Active 100MHz CLK CD/1100 110100 10 0100 Active 60MHz CLK CF/1100 111100 10 0110 Active 30MHz CLK D0/1101 000000 10 0111 Active 10MHz CLK ??Start SEU Test ??Send Back Result ??Memory Test