Presentation on theme: "Digital Phase Follower -- Deserializer in Low-Cost FPGA Jinyuan Wu, Z. Shi."— Presentation transcript:
Digital Phase Follower -- Deserializer in Low-Cost FPGA Jinyuan Wu, Z. Shi
Motivation In HEP systems, sometime many channels of serial data must be concentrated. It will be nice if the data clock is not transmitted separately. (Just transmit a single data channel). It will be nice if it can be received in low-cost FPGA in which dedicated serial data receivers are not available. It will be nice if user protocol can be supported. (Can be 8B/10B, or can be anything users want). Examples: –TSO modules to PP modules. (500 Mbps, user protocol). –FPIX2 to PDCB. (140 Mbps, user protocol).
Receiving Serial Data Data channels are de-serialized using shift registers. The clock for the receiving shift registers comes from: 1.Separate channel. (Channel-channel skew ). 2.Same data channel. –Clock recovery using PLL. (Phase detection+VCO). –Dynamic phase aligner. (In Altera devices, choosing a correct clock phase from 8 phase samples). –Digital phase follower. (For low-cost FPGA).
Multiple Sampling Multiple sampling is used to determine the phase of the data. A correct sampling point is automatically chosen after first 0 to 1 transaction. The sampling point shifts following the shift of the data phase. Everything is in standard digital circuit. b0b1b2 b0b1b2b3 b0b1b2b3b4b5 Quad Sampling Fs = 4/UI Triple Sampling Fs = 3/UI Double Sampling Fs 2/UI
More Notes on Multiple Sampling In digital phase follower, since no clock recovery is needed, 4, 3 or 2 samples per bit (unit interval) are sufficient. (Not 8). In double sampling case, sampling rate must be known either less or larger than 2/UI. b0b1b2 b0b1b2b3 b0b1b2b3b4b5 Quad Sampling Fs = 4/UI Triple Sampling Fs = 3/UI Double Sampling Fs 2/UI
Digital Phase Follower, Block Diagram c0 c90 c180 c270 c0Data In Multiple Sampling Clock Domain Changing b0 b1 Frame Detection Data Out Tri-speed Shift Register Shift2 Shift0 was3 is0 SEL was0 is3 Trans. Detection Q0 Q1 Q2 Q3QF QE QD
Digital Phase Follower: Operation b0 SEL Q0 Q1 Q2 Q3 QF QE QD Newer Samples Older Samples Selected Sample Selected Sample Selected Sample Selected Sample SEL=0SEL=1SEL=2SEL=3
Was 0, Is 3, Data Is Slower. Shift 0. Q0 Q1 Q2 Q3 QF QE QD Old Selection New Selection SEL was 0SEL is 3 b0 b1 Tri-speed Shift Register Shift2 Shift0 was3 is0 SEL was0 is3 Q0 Q1 Q2 Q3 This bit has been sent to the shift register. No duplicate recording. Newer Samples Older Samples
Was 3, Is 0, Data Is Faster. Shift 2. Q0 Q1 Q2 Q3 QF QE QD New Selection Old Selection SEL was 3SEL is 0 b0 b1 Tri-speed Shift Register Shift2 Shift0 was3 is0 SEL was0 is3 Q0 Q1 Q2 Q3 This bit has not been sent to the shift register. Sent it through b1, along with new selection b0=Q0. Newer Samples Older Samples
Simulation (1) This is a 4B/5B receiver working at 400Mbps, compiled in an Altera Cyclone device. The receiving clock is 0.4% slower – no errors is seen.
Simulation (2) The same receiver running with receiving clock 0.4% faster – no errors is seen.
Deserializer Based on Digital Phase Follower Data is self-timed, no separate clock transmission is needed. The transmitter and receiver clocks can be independent – frequency difference is compensated. User protocols are supported. It can be implemented in low-cost FPGA.
Digital Phase Follower Start-up Preamble: 1 idle word with 0 to 1 transitions. –In other scheme, long preambles or training patterns are needed. Frame detection: defined by user. It can be xxxxxxxxxx (in FPIX2). Data: