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TileCal Optical Multiplexer Board 9U VME Prototype Cristobal Cuenca Almenar IFIC (Universitat de Valencia-CSIC)

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Presentation on theme: "TileCal Optical Multiplexer Board 9U VME Prototype Cristobal Cuenca Almenar IFIC (Universitat de Valencia-CSIC)"— Presentation transcript:

1 TileCal Optical Multiplexer Board 9U VME Prototype Cristobal Cuenca Almenar IFIC (Universitat de Valencia-CSIC)

2 Outline Introduction Previous work OMB 6U Final prototype OMB 9U Schedule for production

3 ATLAS detector

4 Optical Multiplexer Board 64 modules x 4 Barrels 2 links out per module with redundant data. Global CRC and DMU CRC. 8 OMBs x 4 crates OMB: 16 In / 8 Out CRC checking VME error counters Data injection to RODs 8 RODs x 4 crates ROD: 8 In/ 2 out Data processing

5 Outline Introduction Previous work OMB 6U Final prototype OMB 9U Schedule for production

6 Previous work OMB 6U Specifications  VME 6U Board format  2 input channels (4 input 640 Mbit/s  2 output channels (2 output fibers)  Digital data analysis (CRC computation)  Trigger and Busy inputs

7 VME_FPGA ALTERA ACEX FPGA EP1K100 VME R/W registers Status/control CRC error registers Provides communication between VME bus and CRC_FPGAs. 2 CRC_FPGAs Altera Cyclone® FPGA Real-time CRC check Internal memory lets us download and inject real events towards the ROD. Event counter generator CRC injection OPTICAL I/O 4 Optical transceivers I/O (Infineon®V23818-K305-L17) 2 Inputs / 1 Output per each CRC_FPGA SERIALIZERS/ DESERIALIZERS 4 receivers (HDMP 1034) 2 transmitters (HDMP1032) The same ones as the I.C.s VME INTERFACE FP connectors LEMO input conectors: Trigger and busy Previous work OMB 6U

8 ROD production with the OMB 6U Front-End emulation with the OMB 6U. Events injected with CRC Online CRC checking  Total events injected: 13 x 10 9 events  Total events checked: 1,7 x 10 9 events

9 Outline Introduction Previous work OMB 6U Final prototype OMB 9U Schedule for production

10 Final prototype OMB 9U Same basic functionality  CRC checking  Data injection  40 MHz clock Differences  8 channels  16 input fibers  8 output fibers  TTCrx  Mezzanine connectors: more processing power?

11 PCB technical specifications PCB details  Input/output signals designed for operation at 80 MHz Standard 9U VME board size 1272 components 2278 nets  10 copper layers  Signal layers between power/gnd planes  Adjacent layers routed orthogonally for minimum coupling

12 OMB main components OPTICAL CONNECTORs (Stratos Lightwave) G_LINKS chips (Agilent HDMP1032/34) 8 CRC FPGAs (Altera CYCLONE 324pins) 4 Processing Units slots VME FPGA (Altera CYCLONE 400pins) TTC FPGA & TTCrx (ALTERA ACEX 144pins)

13 OMB CRC checking 16 Front End inputs. 8 output to ROD Real time CRC checking.  GLOBAL  DMU CRC TTC Information  BCID DMU check Error counters readable from VME.

14 OMB: ROD injector Data injector to RODs.  Actual data  Autogenerated data. Trigger:  External source.  TTC information

15 OMB: Processing Units Upgrade 4 Processing Units. Compatible with ROD PUs. Pre-processing of front end data.

16 Outline Introduction Previous work OMB 6U Final prototype OMB 9U Schedule for production

17 Schedule First prototype validated. Currently producing the second prototype with minor changes Software and firmware adaptation from 6U board. Production of 38 boards during the summer. Installation in the ATLAS cavern at the end of the year.

18 Backup slides

19 Final prototype OMB 9U

20 Signal integrity issues  Big area, not too much populated  Long distance traces (high coupling)  Clock distribution  JTAG chain distribution  VME-CRC FPGA serial bus  Different voltage supplies  +3.3 Volt for FPGA I/O and some logic  +1.5 Volt for FPGA cores (island)  +5 Volt for logic  +12 Volt for NIM/TTL conversion (ext. trigger input)

21 Final prototype OMB 9U Example of SI analysis: VME to CRC serial BUS  Connected between the VME FPGA and all CRC FPGAs  For control, communication, configuration, etc.  4 lines: CLK, DATA0, DATA1, DATA2, DATA3  Frequency of operation 40 MHz

22 Final prototype OMB 9U First attempt  Manual placement and routing of bus lines  Keep stubs short  Keep same routing layer as much as possible  R, RC termination Problem  Characteristic impedance change at T junction  Reflections at first FPGA creates InterSymbol Interference (ISI)

23 Final prototype OMB 9U PostLayout simulation

24 Final prototype OMB 9U Second attempt  Manual placement and routing of bus lines  Keep stubs short  Keep same routing layer as much as possible Problem  Reflections with different termination schemes

25 Final prototype OMB 9U PostLayout simulation

26 Final prototype OMB 9U Final attempt  Manual placement and routing of bus lines  Keep stubs short  Keep same routing layer as much as possible Solution  Resistive termination at both ends

27 Final prototype OMB 9U PostLayout simulation


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