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Trigger System Functions Master/Slave Operation –Located in Readout Boards’ BE-FPGA, but only active as Master in one slot. –Master controls asynchronous.

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Presentation on theme: "Trigger System Functions Master/Slave Operation –Located in Readout Boards’ BE-FPGA, but only active as Master in one slot. –Master controls asynchronous."— Presentation transcript:

1 Trigger System Functions Master/Slave Operation –Located in Readout Boards’ BE-FPGA, but only active as Master in one slot. –Master controls asynchronous Trigger feed-through. –Trigger fanned-out to other Readout Boards via backplane pins and custom connections. –Receives Trigger again as Slave. VME Interface: –Trigger system controlled via VME registers/memory. Digitiser: Stores incoming signals prior to trigger: –Allows pre-trigger ‘environment’ to be stored with event data. Veto Logic: –Inhibits Triggers while busy, protects against double-triggers.

2 Trigger System Functions (Continued) Interfaces to other slots and external devices: –May have back-of-crate card to provide fan-out & connector. –Some signals can generate interrupts (BeamOn/Off). –Able to delay outgoing external Triggers (~5ns steps). Stand-alone functions: –Periodic/Random Trigger, Clock generator. Sequencer/Sink - Play/Record (pre-)trigger events: –16kBytes (clock periods) deep - pending FPGA utilisation. –Good for repeatability and fast trigger testing (sync. only). –Sink stores outgoing signals - provides software testability.

3 4x PreTrigger 1x BeamOn 4x Activity 1x Veto 8x Trigger Delayed Trig 1 Delayed Trig 8 ‘Sequencer’ + ‘Sink’ 16KByte RAM ‘Digitiser’ 32bit Shift Registers (x9) Edge Detect Beam On Sync + Enable 6x Spare 1x Spare SEQ VME Veto Sync + Enable Pre-Trigger Sync + Enables Internal Trig Osc + Randomiser Activity Sync + Enables 4x SR SEQ VME 4x SR SEQ VME SR VME Trigger Gate Generate VME IRQ SEQ VME Width/ Delay Trigger Sync IRQ SINK VME Trigger Latch,Veto START STOP START STOP J2 EXT NIM 16 In J0 LVDS 5 In VME J0 LVDS 2 Out 1x Trigger 1x Clock 3x Spare J2 BP LVDS 8 Out EXT NIM 16 Out 4x Trigger 1x Clock VME 8 x Counter Delays Clock Control BE FPGA - Trigger System 4x Spare VME 40MHz 160MHz (v4 - 22/9/2003) Trigger System Functional Diagram

4 Trigger/Event Data Integration FE-BE Control & Transfer Front-End Data Trigger Processor Pre-Triggers Event Data Store 0102030405 Trigger Data Store 0102030405 Readout Data Block Header Block (Trig)Data Block (Event) Trig Backplane Data Transfer Readout Data Block Select & Build

5 Trigger Status External Interface: Mostly specified. Requires back-of-crate cable/board system finalised. Trigger Processing System: Outline complete. Requirements understood. Overall code structure in place, but nuts-and-bolts not coded. More work required on asynchronous trigger transfer skew. Simulation of not started. Integration with existing firmware: Started. Able to edit existing FED design in HDL Designer. Register Read/Write path understood. Coupling to event data block header not understood.

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