1. Multiplication Discussion 11.1

2. Multiplier Binary Multiplication 4 x 4 Multiplier

3. Binary Multiplication

4. 13 x 12 26 13 156 1101 1100 0000 1101 10011100 9 C = 156

5. Hex Multiplication

6. 61 x 90 5490 3D x 5A 262 A x D = 82, A x 3 = 1E + 8 = 26 131 5 x D = 41, 5 x 3 = F + 4 = 13 1572 16 = 5490 10 Dec Hex

7. Multiplication 13 x11 13 143 = 8Fh 1101 x1011 1101 100111 0000 100111 1101 10001111

8. library IEEE;use IEEE.std_logic_1164.all; package std_logic_arith is type UNSIGNED is array (NATURAL range <>) of STD_LOGIC; type SIGNED is array (NATURAL range <>) of STD_LOGIC; subtype SMALL_INT is INTEGER range 0 to 1; function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED; function "*"(L: SIGNED; R: SIGNED) return SIGNED; function "*"(L: SIGNED; R: UNSIGNED) return SIGNED; function "*"(L: UNSIGNED; R: SIGNED) return SIGNED; function "*"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR; function "*"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR; function "*"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR; function "*"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR; std_logic_arith.vhd

9. function mult(A,B: UNSIGNED) return UNSIGNED is constant msb: integer:=A'length+B'length-1; variable BA: UNSIGNED(msb downto 0); variable PA: UNSIGNED(msb downto 0); begin if (A(A'left) = 'X' or B(B'left) = 'X') then PA := (others => 'X'); return(PA); end if; PA := (others => '0'); BA := CONV_UNSIGNED(B,(A'length+B'length)); for i in 0 to A'length-1 loop if A(i) = '1' then PA := PA+BA; end if; for j in msb downto 1 loop BA(j):=BA(j-1); end loop; BA(0) := '0'; end loop; return(PA); end; 1101 x1011 1101 100111 0000 100111 1101 10001111

10. function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is begin return mult(CONV_UNSIGNED(L, L'length), CONV_UNSIGNED(R, R'length)); end;

11. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; std_logic_unsigned.vhd package STD_LOGIC_UNSIGNED is function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;

12. function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is constant length: INTEGER := maximum(L'length, R'length); variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0); begin result := UNSIGNED(L) * UNSIGNED(R); return std_logic_vector(result); end; library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; package body STD_LOGIC_UNSIGNED is std_logic_unsigned.vhd (cont.)

13. Testing the * operator Use BTN(0) to load SW into Ra and Rb and then display product in Rp Control signals: aload bload pload dmsel m2sel(1:0)

14. Three consecutive pushings of BTN(0) Control signals: aload bload pload dmsel m2sel(1:0)

15. VHDL Canonical Sequential Network State Register Combinational Network x(t) s(t+1) s(t) z(t) clk init present state present input next state present output process(clk, init) process(present_state, x)

16. -- Title: Mult Control Unit library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity mult_control is port ( clr: in STD_LOGIC; clk: in STD_LOGIC; BTN0: in STD_LOGIC; m2sel: out STD_LOGIC_VECTOR (1 downto 0); aload, bload, dmsel: out STD_LOGIC; pload: out STD_LOGIC ); end mult_control;

17. architecture mult_control_arch of mult_control is type state_type is (sA, sB, sC, sD, sE, sF); signal current_state, next_state: state_type; begin C1: process(current_state, BTN0) begin -- Initialize all outputs pload <= '0'; dmsel <= '0'; aload <= '0'; bload <= '0'; m2sel <= "00"; mult_control.vhd

18. case current_state is when sA =>--wait for BTN0 up if BTN0 = '1' then next_state <= sA; m2sel <= "11"; else next_state <= sB; end if; when sB =>--wait for BTN0 down if BTN0 = '1' then next_state <= sC; aload <= '1'; -- A <- SW m2sel <= "00"; else next_state <= sB; m2sel <= "11"; end if;

19. when sC =>--wait for BTN0 up if BTN0 = '1' then next_state <= sC; m2sel <= "00"; else next_state <= sD; end if; when sD =>--wait for BTN0 down if BTN0 = '1' then next_state <= sE; dmsel <= '1'; bload <= '1'; -- B <- SW m2sel <= "01"; else next_state <= sD; m2sel <= "00"; end if;

20. when sE =>--wait for BTN0 up if BTN0 = '1' then next_state <= sE; m2sel <= "01"; else next_state <= sF; end if; when sF =>--wait for BTN0 down if BTN0 = '1' then next_state <= sA; pload <= '1'; m2sel <= "11"; else next_state <= sF; m2sel <= "01"; end if; end case; end process C1;

21. statereg: process(clk, clr)-- the state register begin if clr = '1' then current_state <= sA; elsif (clk'event and clk = '1') then current_state <= next_state; end if; end process statereg; end mult_control_arch;

22. -- Title: Multiply Test library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_unsigned.all; use work.mult_components.all; entity mult is port( mclk : in STD_LOGIC; SW : in STD_LOGIC_VECTOR(7 downto 0); BTN: in STD_LOGIC_VECTOR(3 downto 0); LD: out STD_LOGIC_VECTOR(7 downto 0); AtoG : out STD_LOGIC_VECTOR(6 downto 0); AN : out STD_LOGIC_VECTOR(3 downto 0) ); end mult; mult.vhd

23. architecture mult_arch of mult is signal r, p, pout, x, b16, a16: std_logic_vector(15 downto 0); signal as, bs, ain, bin: std_logic_vector(7 downto 0); signal clr, clk, cclk, bnbuf: std_logic; signal clkdiv: std_logic_vector(23 downto 0); signal aload, bload, pload, dmsel: STD_LOGIC; signal m2sel: STD_LOGIC_VECTOR (1 downto 0); constant bus_width8: positive := 8; constant bus_width16: positive := 16;

24. begin clr <= BTN(3); -- Divide the master clock (50Mhz) process (mclk) begin if mclk = '1' and mclk'Event then clkdiv <= clkdiv + 1; end if; end process; clk <= clkdiv(0);-- 25 MHz cclk <= clkdiv(17);-- 190 Hz

25. a16 <= "00000000" & as; b16 <= "00000000" & bs; p <= as * bs; U1: dmux2g generic map(width => bus_width8) port map (y => SW, a => ain, b => bin, sel => dmsel); U2a: reg generic map(width => bus_width8) port map (d => ain, load => aload, clr => clr, clk =>clk, q => as); U3b: reg generic map(width => bus_width8) port map (d => bin, load => bload, clr => clr, clk =>clk, q => bs); U4p: reg generic map(width => bus_width16) port map (d => p, load => pload, clr => clr, clk =>clk, q => pout);

26. U5: mux4g generic map(width => bus_width16) port map (a => a16, b => b16, c => pout, d => pout, sel => m2sel, y => x); U7: x7segb port map (x => x, cclk => cclk, clr => clr, AtoG => AtoG, AN => AN); U8: mult_control port map (clr => clr, clk => clk, BTN0 => BTN(0), m2sel => m2sel, aload => aload, bload => bload, dmsel => dmsel, pload => pload); LD <= SW; end mult_arch;

27. Recall: Multiplication 13 x11 13 143 = 8Fh 1101 x1011 1101 100111 0000 100111 1101 10001111

28. Multi-cycle Multiplication 1101 x1011 1101 100111 0000 100111 1101 10001111 1101 00001011 01101101 adsh 1101 10011110 adsh 1001111 sh 1101 10001111 adsh

29. Multiplication UM* ( u1 u2 -- upL upH ) R1R2 R3 mpp (multiply partial product) if R2(0) = 1 then adsh else sh end if; All other signed and unsigned multiplication can be derived from this Multiplicand Multiplier Zeros

30. variable AVector: STD_LOGIC_VECTOR (width downto 0); variable BVector: STD_LOGIC_VECTOR (width downto 0); variable CVector: STD_LOGIC_VECTOR (width downto 0); variable yVector: STD_LOGIC_VECTOR (width downto 0); variable y1_tmp: STD_LOGIC_VECTOR (width-1 downto 0); AVector := '0' & a; BVector := '0' & b; CVector := '0' & c; y1_tmp := false; yVector := '0' & false; begin R1 (C)R2 (B) R3 (A)

31. -- mpp if b(0) = '1' then yVector := AVector + CVector; else yVector := AVector; end if; y <= yVector(width downto 1); y1 <= yVector(0) & b(width-1 downto 1); mpp (multiply partial product) if R2(0) = 1 then adsh else sh end if; R1 (C)R2 (B) R3 (A)

32. UM* ( u1 u2 - upL upH ) mpp mpp 16 x 16 = 32 Multiplication Top Level