 Ring Counter Discussion D5.3 Example 32. Ring Counter if rising_edge(CLK) then for i in 0 to 2 loop s(i) <= s(i+1); end loop; s(3) <= s(0); end if; Behavior.

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Ring Counter Discussion D5.3 Example 32

Ring Counter if rising_edge(CLK) then for i in 0 to 2 loop s(i) <= s(i+1); end loop; s(3) <= s(0); end if; Behavior s(3) s(2) s(1) s(0) Note: Must use signals here

library IEEE; use IEEE.STD_LOGIC_1164.all; entity ring4 is port( clk : in STD_LOGIC; reset : in STD_LOGIC; Q : out STD_LOGIC_VECTOR(3 downto 0) ); end ring4; architecture ring4 of ring4 is signal s: STD_LOGIC_VECTOR(3 downto 0); begin process(reset,clk) begin if reset = '1' then s <= "0001"; elsif clk'event and clk = '1' then for i in 0 to 2 loop s(i) <= s(i+1); end loop; s(3) <= s(0); end if; end process; Q <= s; end ring4; ring4.vhd Note: Must use signals here

ring4 simulation

A Random Number Generator if rising_edge(CLK) then for i in 0 to 2 loop s(i) <= s(i+1); end loop; s(3) <= s(0) xor s(3); end if; Behavior s(3) s(2) s(1) s(0)

Q3 Q2 Q1 Q0 0 0 0 1 1 1 0 0 0 8 1 1 0 0 C 1 1 1 0 E 1 1 1 1 F 0 1 1 1 7 1 0 1 1 B 0 1 0 1 5 Q3 Q2 Q1 Q0 1 0 1 0 A 1 1 0 1 D 0 1 1 0 6 0 0 1 1 3 1 0 0 1 9 0 1 0 0 4 0 0 1 0 2 0 0 0 1 1

library IEEE; use IEEE.STD_LOGIC_1164.all; entity rand4 is port( clk : in STD_LOGIC; reset : in STD_LOGIC; Q : out STD_LOGIC_VECTOR(3 downto 0) ); end rand4 ; architecture rand4 of rand4 is signal s: STD_LOGIC_VECTOR(3 downto 0); begin process(reset,clk) begin if reset = '1' then s <= "0001"; elsif clk'event and clk = '1' then for i in 0 to 2 loop s(i) <= s(i+1); end loop; s(3) <= s(0) xor s(3); end if; end process; Q <= s; end rand4; rand4.vhd

rand4 simulation

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