Presentation is loading. Please wait.

Presentation is loading. Please wait.

A Simple Microcontroller VHDL Tutorial R. E. Haskell and D. M. Hanna T6: VHDL State Machines.

Published by Modified over 8 years ago

Similar presentations

Presentation on theme: "A Simple Microcontroller VHDL Tutorial R. E. Haskell and D. M. Hanna T6: VHDL State Machines."— Presentation transcript:

1 A Simple Microcontroller VHDL Tutorial R. E. Haskell and D. M. Hanna T6: VHDL State Machines

2 The T8X Microcontroller

3 PC.vhd library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity PC is port ( d: in STD_LOGIC_VECTOR (7 downto 0); clr: in STD_LOGIC; clk: in STD_LOGIC; inc: in STD_LOGIC; pload: in STD_LOGIC; q: out STD_LOGIC_VECTOR (7 downto 0) ); end PC;

4 architecture PC_arch of PC is begin process (clk, clr) variable COUNT: STD_LOGIC_VECTOR (7 downto 0); begin if clr = '1' then COUNT := "00000000"; q <= COUNT; elsif clk'event and clk='1' then if pload = '0' then if inc = '1' then COUNT := COUNT + 1; end if; else COUNT := d; end if; q <= COUNT; end if; end process; end PC_arch;

5 Tcodes.vhd package tcodes is subtype opcode is std_logic_vector(7 downto 0); -- Register instructions --WHYP WORDS constant nop:opcode := X"00";-- NOP constant dup: opcode := X"01";-- DUP -- ALU instructions constant plus: opcode := X"10"; -- + constant plus1: opcode := X"11"; -- 1+ constant invert: opcode := X"12"; -- INVERT constant twotimes: opcode := X"13"; -- 2*

6 -- Return Stack, Memory Access, and I/O instructions constant swfetch: opcode := X"31"; -- SW@ constant digstore: opcode := X"32"; -- DIG! -- Transfer instructions constant jmp: opcode := X"40"; -- GOTO constant jnbtn4: opcode := X"41";-- WAIT_BTN2_UP constant jbtn4: opcode := X"42"; -- IF_BTN4 end tcodes;

7 fetch exec exec_ fetch M(6)=‘1’ M(6)=‘0’ M(6)=‘1’ -- Transfer instructions constant jmp: opcode := X"40"; -- GOTO constant jnbtn4: opcode := X"41";-- WAIT_BTN2_UP constant jbtn4: opcode := X"42"; -- IF_BTN4

8 VHDL Finite State Machine State Register C1 x(t) s(t+1) s(t) z(t) clk clr present state next state C2 process(clk, clr) process(present_state, x)

9 Tcontrol State Machine State Register C1 instr s(t+1) s(t) clk clr current state next state C2 process(clk, clr) process(current_state, M) process(current_state, instr) M

10 architecture Tcontrol_arch of Tcontrol is type state_type is (fetch, exec, exec_fetch); signal current_state, next_state: state_type; synch: process(clk, clr) begin if clr = '1' then current_state <= fetch; elsif (clk'event and clk = '1') then current_state <= next_state; end if; end process synch;

11 C1: process(current_state, M) begin case current_state is when fetch => if M(6) = ‘1’ then next_state <= exec; else next_state <= exec_fetch; end if; when exec_fetch => if M(6) = ‘1’ then next_state <= exec; else next_state <= exec_fetch; end if; when exec => next_state <= fetch; end case; end process C1; fetch exec exec_ fetch M(6)=‘1’ M(6)=‘0’ M(6)=‘1’

12 Tcontrol State Machine State Register C1 instr s(t+1) s(t) clk clr current state next state C2 process(clk, clr) process(current_state, M) process(current_state, instr) M

13 C2: process(instr, current_state) begin alusel <= "00"; msel <= "00"; pload <= '0'; tload <= '0'; nload <= '0'; digload <= '0'; inc <= '1'; iload <= '0'; if (current_state = fetch) or (current_state = exec_fetch) then iload <= '1'; -- fetch next instruction end if; if (current_state = exec) or (current_state = exec_fetch) then case instr is when nop => null; when dup => nload <= '1';

14 when plus => tload <= '1'; when plus1 => tload <= '1'; alusel <= "01"; when invert => tload <= '1'; alusel <= "10"; when twotimes => tload <= '1'; alusel <= "11"; when swfetch => tload <= '1'; msel <= "01"; when digstore => digload <= '1'; when jmp => pload <= '1'; inc <= '0'; when jnbtn4 => pload <= not BTN(4); inc <= BTN(4); when jbtn4 => pload <= BTN(4); inc <= not BTN(4); when others => null; end case; end if; end process C2;

15 T6 Lab Exercise Multiply switch setting by 10 and display hex result on 7-segment display. BEGIN WAIT_BTN4\ wait to press BTN4 SW@\ read SW(1:8) n DIG!\ 7-segment display WAIT_BTN4\ n 2*\ 2n DUP\ 2n 2n 2*\ 2n 4n 2*\ 2n 8n +\ 10n DIG!\ 7-segment display AGAIN ;

16 Trom6.vhd library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use work.tcodes.all; entity Trom6 is port ( addr: in STD_LOGIC_VECTOR (7 downto 0); M: out STD_LOGIC_VECTOR (7 downto 0) ); end Trom6;

17 architecture Trom6_arch of Trom6 is subtype tword is std_logic_vector(7 downto 0); type rom_array is array (0 to 18) of tword; constant rom: rom_array := ( JBTN4, X"00",-- X"00" wait for BTN4 up JNBTN4, X"02",-- X"02" wait for BTN4 SWFETCH,-- X"04" push switches digstore,-- X"05" display JBTN4, X"06",-- X"06" wait for BTN4 up JNBTN4, X"08",-- X"08" wait for BTN4 twotimes,-- X"0A" 2* DUP,-- X"0B" DUP twotimes,-- X"0C" 2* twotimes,-- X"0D" 2* plus,-- X"0E" + digstore,-- X"0F" display JMP, X"00",-- X"10" GOTO 0 X"00"-- X"12" );

18 T6 Lab Exercise File T6comp.vhd is a package that contains the component declarations for all components in the T8X microcontroller. File T6main.vhd is the top-level design of the T8X microcontroller.

19 T6 Lab Exercise: The T8X Microcontoller

20 T6main.vhd library IEEE; use IEEE.std_logic_1164.all; use work.T6comp.all; entity T6main is port ( SW: in STD_LOGIC_VECTOR (1 to 8); BTN: in STD_LOGIC_VECTOR (1 to 4); LD: out STD_LOGIC_VECTOR (1 to 8); AtoG: out STD_LOGIC_VECTOR (6 downto 0); A: out STD_LOGIC_VECTOR (3 downto 0) ); end T6main;

21 T6main.vhd (cont.) architecture T6main_arch of T6main is signal tin, T, N, y, P, M, instr: std_logic_vector(7 downto 0); signal clr, clk: std_logic; signal pload, iload, tload, nload, digload, inc: std_logic; signal msel, alusel : std_logic_vector(1 downto 0); signal GND: std_logic_vector(3 downto 0); begin

22 GND <= "0000"; U0: mux4 port map (a => y, b =>SW, c(3 downto 0) => BTN, c(7 downto 4) => GND, d => M, sel => msel, y => tin); Treg: reg port map (d => tin, load =>tload, clr => clr, clk =>clk, q => T); Nreg: reg port map (d => T, load => nload, clr => clr, clk =>clk, q => N); U1: alu port map (a => T, b => N, sel => alusel, y => y); U2: digdisplay port map (T => T, N => N, digload => digload, clr => clr, clk => clk, A => A, AtoG => AtoG); T6main.vhd (cont.)

23 U3: PC port map (d => M, clr => clr, clk => clk, pload => pload, inc => inc, q => P); U4: Trom6 port map (addr => P, M => M); ireg: reg port map (d => M, load => iload, clr => clr, clk =>clk, q => instr); U5: Tcontrol port map (instr => instr, M => M, clr => clr, clk => clk, BTN => BTN, alusel => alusel, msel => msel, inc => inc, pload => pload, tload => tload, nload => nload, digload => digload, iload => iload); U6: osc_4k port map (clk => clk); LD <= SW; clr <= BTN(1); end T6main_arch; T6main.vhd (cont.)

Download ppt "A Simple Microcontroller VHDL Tutorial R. E. Haskell and D. M. Hanna T6: VHDL State Machines."

Similar presentations

Arbitrary Waveform Discussion 5.5 Example 34.

Arbitrary Waveform Discussion 5.5 Example 34.
7-Segment Display: Spartan-3 board

7-Segment Display: Spartan-3 board
1 VLSI DESIGN USING VHDL Part II A workshop by Dr. Junaid Ahmed Zubairi.

1 VLSI DESIGN USING VHDL Part II A workshop by Dr. Junaid Ahmed Zubairi.
Ring Counter Discussion D5.3 Example 32. Ring Counter if rising_edge(CLK) then for i in 0 to 2 loop s(i)

Ring Counter Discussion D5.3 Example 32. Ring Counter if rising_edge(CLK) then for i in 0 to 2 loop s(i)
Top-level VHDL Designs

Top-level VHDL Designs
Multiplication Discussion 11.1. Multiplier Binary Multiplication 4 x 4 Multiplier.

Multiplication Discussion Multiplier Binary Multiplication 4 x 4 Multiplier.
Registers VHDL Tutorial R. E. Haskell and D. M. Hanna T2: Sequential Logic Circuits.

Registers VHDL Tutorial R. E. Haskell and D. M. Hanna T2: Sequential Logic Circuits.
RS-232 Port Discussion D7.1. Loop feedback RS-232 voltage levels: +5.5 V (logic 0) -5.5 V (logic 1)

RS-232 Port Discussion D7.1. Loop feedback RS-232 voltage levels: +5.5 V (logic 0) -5.5 V (logic 1)
Data Stack Lecture 8.2 A VHDL Forth Core for FPGAs: Sect. 3.

Data Stack Lecture 8.2 A VHDL Forth Core for FPGAs: Sect. 3.
Integer Square Root.

Integer Square Root.
Single-Cycle Instructions VHDL Tutorial R. E. Haskell and D. M. Hanna T5: VHDL ROM.

Single-Cycle Instructions VHDL Tutorial R. E. Haskell and D. M. Hanna T5: VHDL ROM.
Digilent Spartan 3 Board Lecture L2.2

Digilent Spartan 3 Board Lecture L2.2
Multi-Base Calculator CSE378 Final Project By Matthew Lehn & Yanqing Zhu December 17, 2001 Professor Haskell.

Multi-Base Calculator CSE378 Final Project By Matthew Lehn & Yanqing Zhu December 17, 2001 Professor Haskell.
FPGAs and VHDL Lecture L12.1. FPGAs and VHDL Field Programmable Gate Arrays (FPGAs) VHDL –2 x 1 MUX –4 x 1 MUX –An Adder –Binary-to-BCD Converter –A Register.

FPGAs and VHDL Lecture L12.1. FPGAs and VHDL Field Programmable Gate Arrays (FPGAs) VHDL –2 x 1 MUX –4 x 1 MUX –An Adder –Binary-to-BCD Converter –A Register.
Structural VHDL VHDL Tutorial R. E. Haskell and D. M. Hanna T3: ALU Design.

Structural VHDL VHDL Tutorial R. E. Haskell and D. M. Hanna T3: ALU Design.
Counters Discussion D5.3 Example 33. Counters 3-Bit, Divide-by-8 Counter 3-Bit Behavioral Counter in Verilog Modulo-5 Counter An N-Bit Counter.

Counters Discussion D5.3 Example 33. Counters 3-Bit, Divide-by-8 Counter 3-Bit Behavioral Counter in Verilog Modulo-5 Counter An N-Bit Counter.
Lab 6 Program Counter and Program ROM Mano & Kime Sections 7-1 – 7-6.

Lab 6 Program Counter and Program ROM Mano & Kime Sections 7-1 – 7-6.
Finite State Machines Discussion D7.1 Mealy and Moore Machines.

Finite State Machines Discussion D7.1 Mealy and Moore Machines.
Multiplication Discussion 11.2. Multiplier Binary Multiplication 4 x 4 Multiplier.

Multiplication Discussion Multiplier Binary Multiplication 4 x 4 Multiplier.
Introduction to VHDL Multiplexers. Introduction to VHDL VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language.

Introduction to VHDL Multiplexers. Introduction to VHDL VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language.

Similar presentations

Ads by Google