1. EECE476: Computer Architecture Lectures 1, 2: Instruction Set Architecture Chapters 1, 2 The University of British ColumbiaEECE 476© 2005 Guy Lemieux

2. 2 REVIEW: What is Instruction Set Architecture? Important acronym: ISA –Instruction Set Architecture The low-level software interface to the machine –Language of the machine –Must translate any programming language into this language –Examples: IA-32 (Intel instruction set), MIPS, SPARC, Alpha, PA-RISC, PowerPC, … Visible to programmer (if desired)!

3. 3 REVIEW: Instruction Set Architecture I/O systemInstr. Set Proc. Compiler Operating System Application Digital Design Circuit Design Instruction Set Architecture Firmware Datapath & Control Layout Software Hardware

4. 4 Which ISA? Millions of Processors Year

5. 5 MIPS CPU –What does MIPS mean? Millions of Instructions Per Second Meaningless Indicator of Processor Speed Microprocessor without Interlocking Pipeline Stages Altera NIOS II CPU –What does NIOS mean?

6. 6 Levels of Representation High Level Language Program Assembly Language Program Machine Language Program Control Signal Specification Compiler Assembler Machine Interpretation temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; lw$15,0($2) lw$16,4($2) sw$16,0($2) sw$15,4($2) 1000 1100 0110 0010 0000 0000 0000 0000 1000 1100 1111 0010 0000 0000 0000 0100 1010 1100 1111 0010 0000 0000 0000 0000 1010 1100 0110 0010 0000 0000 0000 0100 °°°° ALUOP[0:3] ← InstrReg[9:12] & MASK

7. 7 Instruction Set Architectures Computer architect’s jargon: ISA –Machine’s native language (not assembly language!) –Interface specification between hardware and low-level software –Includes: language mnemonics (syntax) behaviour (semantics) instruction format (bit encoding) –Note: assembler is simple translator (assembly langage -> machine language) Standardizes instructions, machine language bit patterns, etc –Advantage: different CPU implementations of the same ISA –Disadvantage: sometimes prevents use of new innovations Many different ISAs –One for every CPU family –Most are very similar, easy to learn a new one!

8. 8 Advantage of Standardized ISA Performance Year

9. 9 Data MovementLoad (from memory) Store (to memory) memory-to-memory move register-to-register move input (from I/O device) output (to I/O device) push, pop (to/from stack) Arithmeticinteger (binary + decimal) or FP Add, Subtract, Multiply, Divide Logicalnot, and, or, set, clear Shiftshift left/right, rotate left/right Control (Jump/Branch)unconditional, conditional Subroutine Linkagecall, return Interrupttrap, return Synchronizationtest & set (atomic read-modify-write) Typical ISA Operations (little change since 1960s)

10. 10 Typical ISA Operations (biggest changes since 1960s) Instruction types eliminated Instruction types added Stringsearch, translate “Multimedia” SIMD Instructions (eg, MMX, 3DNow, SSE) parallel subword ops (eg 4-way 16bit add with 1 instruction) Looping Conditional Executioneliminates branch instructions p = (b>c); // comparison If(p) a=b; // conditional move If(!p) a=c; // conditional move

11. 11 Top 10 IA-32 Instructions RankInstructionInteger Average (Percent total executed) 1load22% 2conditional branch20% 3compare16% 4store12% 5add8% 6and6% 7sub5% 8move register-register4% 9call1% 10return1% Total96% Simple instructions dominate instruction frequency

12. 12 Top MIPS Instructions

13. 13 ISA Summary Support these simple instructions, since they will dominate the number of instructions executed: load, store, add, subtract, move register-register, and, shift, compare equal, compare not equal, branch, jump, call, return;

14. 14 Compilers and Instruction Set Architectures Designing a new ISA? Design Choices… Ease of compilation: orthogonality: no special registers, no special cases, all operations work with all registers, all operand modes available with any data type or instruction type completeness: supports wide range of operations and target applications regularity: no overloading or multiple-meanings of instruction fields streamlined: resource needs are easily determined Eg, all instructions same length Eg, no “fancy” instructions that make it difficult to know if the ALU will be used

15. 15 Good (Simple) Compiler Considerations Lessons from history…. –Provide at least 16 general purpose registers plus separate floating-point registers Register Assignment (of variables to registers) is critical too Easier if lots of registers Too many registers slows down CPU clock speed –Be sure all addressing modes apply to all data transfer instructions –Aim for a minimalist instruction set

16. 16 simple instructions all 32 bits wide very structured, no unnecessary baggage only three instruction formats: rely on compiler to achieve performance — what are the compiler's goals? help compiler where we can op rs rt rdshamtfunct op rs rt Imm16 op Imm26 RIJRIJ Overview of MIPS Instructions 031

17. 17 MIPS I Operation Overview Arithmetic/Logical/Comparisons –Add, AddU, Sub, SubU, And, Or, Xor, Nor –AddI, AddIU, AndI, OrI, XorI, LUI –SLT, SLTU, SLTI, SLTIU, –SLL, SRL, SRA, SLLV, SRLV, SRAV Memory Access –LB, LBU, LH, LHU, LW, LWL, LWR –SB, SH, SW, SWL, SWR

18. 18 MIPS Arithmetic All instructions have 3 operands –R-type instructions (think “R=register”) Operand order is fixed (destination first) Example: C code: A = B + C MIPS code: add $s0, $s1, $s2 (registers associated with variables by compiler)

19. 19 MIPS Arithmetic C to MIPS Assembly Example C code: A = B + C + D; E = F - A; MIPS code: add $t0, $s1, $s2 add $s0, $t0, $s3 sub $s4, $s5, $s0 –Operands must be registers, only 32 registers provided –Notice our convention $s0..$s7 registers hold C language variables $t0..$t9 registers hold intermediate results

20. 20 Registers vs. Memory Arithmetic instructions operands must be registers –Only 32 registers provided –Cannot “add value to memory location X” –Can only “add register B and register C, store in register A” Compiler associates variables with registers Q: What about programs with lots of variables? –A: Load/save registers from/to memory –Called register spilling

21. MIPS Registers: Software Conventions for Register Use

22. 22 0zero constant 0 1atreserved for assembler 2v0expression evaluation & 3v1function results 4a0arguments 5a1 6a2 7a3 8t0temporary: caller saves if they are important...(callee can clobber) 15t7 MIPS: Software Conventions for Registers 16s0callee saves (if used)... (caller can clobber on return) 23s7 24t8 temporary (cont’d) 25t9 26k0reserved for OS kernel 27k1 28gpPointer to global area 29spStack pointer 30fpFrame pointer 31raReturn Address (HW)

23. 23 Caller/Callee Relationship Caller function runs first –Calls the “callee” as sub-function Analogy –Caller == Employer –Callee == Employee int caller() { int a,b; b = callee(a); return b; } int callee(int t) { int x=2, y=3; return x+y+t; }

24. 24 Caller/Callee Saved Registers No such thing as “local variables” and “global variables” in MIPS ISA All registers are “global” Conventions –$t0-$t9 registers Callee temporary variables Callee can use freely Do not expect same value in these registers after function call Almost never saved to memory, short-term use only –$s0-$s7 registers Callee must save before use Caller relies upon callee to restore these values before returning // globally visible registers int t0, t1,..., t7, t8, t9; int s0, s1,..., s7; int caller() { t0 = 1; s0 = t0 + 1; callee(); // s0 == 2 here, always // t0 = ? unreliable value } int callee() { // callee saves $s0-$s7 save_s_regs(); t0 = calcB(s0,s1,t9,t3); s0 = 0; restore_s_regs(); }

25. 25 Memory Organization: Bytes Large one-dimensional array of bytes Each byte has unique address Memory address is index into the array “Byte addressing” –Each different address points to a unique byte of memory. 6 5 4 3 2 1 0 8 bits of data... Byte address

26. 26 Memory Organization: Words Bytes are nice, but most data items use larger “words” For MIPS, a word is 32 bits (4 bytes) 2 32 bytes with byte addresses from 0 to 2 32 -1 2 30 words starting at byte addresses 0, 4, 8,... 2 32 -4 Words are aligned –The 2 least-significant bits of a word’s byte address are always zero 12 8 4 0... 32 bits of data Each register holds 32 bits of data (1 word) Byte address

27. 27 Memory Endian-ness Big Endian, aka “Motorola” –MSB comes first (lower byte address is MSB) Little Endian, aka “Intel” –LSB comes first (lower byte address is LSB) MIPS is “Big Endian” –(actually, it is configurable, but we shall use Big Endian) MSB...…LSB MSB...LSB MSB...…LSB MSB...…LSB MSB...…LSB MSB...LSB MSB...…LSB MSB...…LSB 0 4 8 12 Byte Address Of Word +0+1+2+3 +2+1+0 …… Byte address 4+2 = 6Byte address 4+1 = 5 Big Endian Little Endian Byte Address Offset

28. 28 Instructions Load and store instructions Example with integers (words): C code: A[8] = h + A[8]; MIPS code: lw $t0, 32($s3) add $t0, $s2, $t0 sw $t0, 32($s3) Store word has destination last Again, arithmetic operands are registers, not memory!

29. 29 Subroutine Example Can we figure out the code? No multiply? Use add instead: swap(int v[], int k); { int temp; temp = v[k] v[k] = v[k+1]; v[k+1] = temp; } swap: muli $2, $5, 4 add $2, $4, $2 lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31 swap: add $2, $5, $5 add $2, $2, $2

30. 30 So far we’ve learned: MIPS –Loads words, but addresses bytes –Arithmetic on registers only InstructionMeaning add $s1, $s2, $s3$s1 = $s2 + $s3 sub $s1, $s2, $s3$s1 = $s2 – $s3 lw $s1, 100($s2)$s1 = Mem[$s2+100] sw $s1, 100($s2)Mem[$s2+100] = $s1

31. 31 Instructions, like registers and words of data, are also 32 bits long –Example: add $t0, $s1, $s2 –Registers have numbers: $t0=8, $s1=17, $s2=18 Instruction Format: R-type (aRithmetic, Register operands) 000000 10001 10010 01000 00000 100000 op rs rt rd shamt funct $s1 $s2 $t0 add What do the field names stand for? MIPS Machine Language bit 0bit 31

32. 32 Instruction Format: I-type (Immediate data) Example: lw $t0, 32($s2) 35 18 8 32 op rs rt Imm16 lw $s2 $t0 32 MIPS Machine Language

33. 33 Decision making instructions –alter the control flow, –i.e., change the "next" instruction to be executed MIPS conditional branch instructions: bne $t0, $t1, Label beq $t0, $t1, Label Example: if (i==j) h = i + j; bne $s0, $s1, Label add $s2, $s0, $s1 Label:.... Control: Branches

34. 34 MIPS unconditional branch instructions: j label Example: if (i!=j) beq $s4, $s5, Lab1 h=i+j; add $s3, $s4, $s5 else jLab2 h=i-j;Lab1: sub $s3, $s4, $s5 Lab2:... Control: Jumps

35. 35 Exercise Write the assembly code for a simple loop for( i=0; i!=a; i=i+1) a=a-1; Assuming initial conditions register $s0 holds i (already =0) register $s1 holds the constant 1 register $s2 holds a (already =10) Solution: Loop:beq $s0, $s2, Done sub $s2, $s2, $s1 add $s0, $s0, $s1 j Loop Done:...