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CEG3420 Lec2.1 ©UCB Fall 1997 ISA Review CEG3420 Computer Design Lecture 2
CEG3420 Lec2.2 ©UCB Fall 1997 Instruction Set Architecture: What Must be Specified? Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction ° Instruction Format or Encoding – how is it decoded? ° Location of operands and result – where other than memory? – how many explicit operands? – how are memory operands located? – which can or cannot be in memory? ° Data type and Size ° Operations – what are supported ° Successor instruction – jumps, conditions, branches - fetch-decode-execute is implicit!
CEG3420 Lec2.3 ©UCB Fall 1997 Basic ISA Classes Accumulator (1 register): 1 addressadd Aacc acc + mem[A] 1+x addressaddx Aacc acc + mem[A + x] Stack: 0 addressaddtos tos + next General Purpose Register: 2 addressadd A B EA(A) EA(A) + EA(B) 3 addressadd A B CEA(A) EA(B) + EA(C) Load/Store: 3 addressadd Ra Rb RcRa Rb + Rc load Ra RbRa mem[Rb] store Ra Rbmem[Rb] Ra Comparison: Bytes per instruction? Number of Instructions? Cycles per instruction?
CEG3420 Lec2.4 ©UCB Fall 1997
CEG3420 Lec2.5 ©UCB Fall 1997 General Purpose Registers Dominate ° all machines use general purpose registers °Advantages of registers registers are faster than memory registers are easier for a compiler to use -e.g., (A*B) – (C*D) – (E*F) can do multiplies in any order vs. stack registers can hold variables -memory traffic is reduced, so program is sped up (since registers are faster than memory) -code density improves (since register named with fewer bits than memory location)
CEG3420 Lec2.6 ©UCB Fall 1997 Summary on Instruction Classes ° Expect new instruction set architecture to use general purpose register Pipelining => Expect it to use load store variant of GPR ISA
CEG3420 Lec2.7 ©UCB Fall 1997 MIPS I Registers °Programmable storage 2^32 x bytes of memory 31 x 32-bit GPRs (R0 = 0) 32 x 32-bit FP registers PC - program counter lo hi - multiplier output registers
CEG3420 Lec2.8 ©UCB Fall 1997 Memory Addressing ° Since 1980 almost every machine uses addresses to level of 8-bits (byte) ° 2 questions for design of ISA: Can read a 32-bit word as four loads of bytes from sequential byte addresses or as one load word from a single byte address How do byte addresses map onto words? Can a word be placed on any byte boundary?
CEG3420 Lec2.9 ©UCB Fall 1997 Addressing Objects: Endianess and Alignment °Big Endian: address of most significant: IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA °Little Endian: address of least significant: Intel 80x86, DEC Vax, DEC Alpha (Windows NT) msblsb little endian byte big endian byte 0 Alignment: require that objects fall on address that is multiple of their size Aligned Not Aligned
CEG3420 Lec2.10 ©UCB Fall 1997 Addressing Modes Addressing modeExampleMeaning RegisterAdd R4,R3R4 R4+R3 ImmediateAdd R4,#3R4 R4+3 DisplacementAdd R4,100(R1)R4 R4+Mem[100+R1] Register indirectAdd R4,(R1)R4 R4+Mem[R1] Indexed / BaseAdd R3,(R1+R2)R3 R3+Mem[R1+R2] Direct or absoluteAdd R1,(1001)R1 R1+Mem Memory indirectAdd R1+Mem[Mem[R3]] Auto-incrementAdd R1,(R2)+R1 R1+Mem[R2]; R2 R2+d Auto-decrementAdd R1,–(R2)R2 R2–d; R1 R1+Mem[R2] Scaled Add R1,100(R2)[R3]R1 R1+Mem[100+R2+R3*d] Why Auto-increment/decrement? Scaled?
CEG3420 Lec2.11 ©UCB Fall 1997 Addressing Mode Usage? (ignore register mode) 3 programs measured on machine with all addressing modes --- Displacement 42% avg, 32% to 66% 75% --- Immediate: 33% avg, 17% to 43% 88% --- Register deferred (indirect): 13% avg, 3% to 24% --- Scaled: 7% avg, 0% to 16% --- Memory indirect: 3% avg, 1% to 6% --- Misc:2% avg, 0% to 3% 75% displacement & immediate 88% displacement, immediate & register indirect
CEG3420 Lec2.12 ©UCB Fall 1997 Displacement Address Size? °Avg. of 5 SPECint92 programs v. avg. 5 SPECfp92 programs °X-axis is in powers of 2: 4 => addresses > 2 3 (8) and (16) °1% of addresses > 16-bits ° bits of displacement needed Address Bits
CEG3420 Lec2.13 ©UCB Fall 1997 Immediate Size? 50% to 60% fit within 8 bits 75% to 80% fit within 16 bits
CEG3420 Lec2.14 ©UCB Fall 1997 Addressing Summary Data Addressing modes that are important: Displacement, Immediate, Register Indirect Displacement size should be 12 to 16 bits Immediate size should be 8 to 16 bits
CEG3420 Lec2.15 ©UCB Fall 1997 Generic Examples of Instruction Format Widths Variable: Fixed: Hybrid: … …
CEG3420 Lec2.16 ©UCB Fall 1997 Summary of Instruction Formats If code size is most important, use variable length instructions If performance is most important, use fixed length instructions Recent embedded machines (ARM, MIPS) added optional mode to execute subset of 16-bit wide instructions (Thumb, MIPS16); per procedure decide performance or density
CEG3420 Lec2.17 ©UCB Fall 1997 Instruction Format If have many memory operands per instructions and many addressing modes, =>Address specifier per operand If have load-store machine with 1 address per instr. and one or two addressing modes, => encode addressing mode in the opcode
CEG3420 Lec2.18 ©UCB Fall 1997 MIPS Addressing Modes/Instruction Formats oprsrtrd immed register Register (direct) oprsrt register Base+index + Memory immedoprsrt Immediate immedoprsrt PC PC-relative + Memory All instructions 32 bits wide Register Indirect?
CEG3420 Lec2.19 ©UCB Fall 1997 Typical Operations (little change since 1960) Data MovementLoad (from memory) Store (to memory) memory-to-memory move register-to-register move input (from I/O device) output (to I/O device) push, pop (to/from stack) Arithmeticinteger (binary + decimal) or FP Add, Subtract, Multiply, Divide Logicalnot, and, or, set, clear Shiftshift left/right, rotate left/right Control (Jump/Branch)unconditional, conditional Subroutine Linkagecall, return Interrupttrap, return Synchronizationtest & set (atomic r-m-w) Stringsearch, translate Multimedia (MMX)parallel subword ops (4 16bit add)
CEG3420 Lec2.20 ©UCB Fall 1997 Top 10 80x86 Instructions
CEG3420 Lec2.21 ©UCB Fall 1997 Operation Summary Support these simple instructions, since they will dominate the number of instructions executed: load, store, add, subtract, move register-register, and, shift, compare equal, compare not equal, branch, jump, call, return;
CEG3420 Lec2.22 ©UCB Fall 1997 Compilers and Instruction Set Architectures Ease of compilation ° orthogonality: no special registers, few special cases, all operand modes available with any data type or instruction type ° completeness: support for a wide range of operations and target applications ° regularity: no overloading for the meanings of instruction fields ° streamlined: resource needs easily determined Register Assignment is critical too ° Easier if lots of registers
CEG3420 Lec2.23 ©UCB Fall 1997 Summary of Compiler Considerations Provide at least 16 general purpose registers plus separate floating-point registers, Be sure all addressing modes apply to all data transfer instructions, Aim for a minimalist instruction set.
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