Download presentation

Presentation is loading. Please wait.

Published bySavannah Tyson Modified over 2 years ago

1
Copyright 2001, Agrawal & BushnellLecture 2 Yield & Quality1 VLSI Testing Lecture 2: Yield & Quality n Yield and manufacturing cost n Clustered defect yield formula n Defect level n Test data analysis n Example: SEMATECH chip n Summary n Problems to solve

2
Copyright 2001, Agrawal & BushnellLecture 2 Yield & Quality2 VLSI Chip Yield n A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by errors in the fabrication process. n A chip with no manufacturing defect is called a good chip. n Fraction (or percentage) of good chips produced in a manufacturing process is called the yield. Yield is denoted by symbol Y. n Cost of a chip: Cost of fabricating and testing a wafer ——————————————————————— Yield x Number of chip sites on the wafer

3
Copyright 2001, Agrawal & BushnellLecture 2 Yield & Quality3 Clustered VLSI Defects Wafer Defects Faulty chips Good chips Unclustered defects Wafer yield = 12/22 = 0.55 Clustered defects (VLSI) Wafer yield = 17/22 = 0.77

4
Copyright 2001, Agrawal & BushnellLecture 2 Yield & Quality4 Yield Parameters n Defect density (d ) = Average number of defects per unit of chip area n Chip area (A) n Clustering parameter (α) Negative binomial distribution of defects, p (x ) = Prob (number of defects on a chip = x ) ( +x ) (Ad / ) x = -------------. ---------------------- x ! ( ) (1+Ad / ) +x where Γ is the gamma function = 0, p (x ) is a delta function (maximum clustering) = ∞, p (x ) is Poisson distribution (no clustering)

5
Copyright 2001, Agrawal & BushnellLecture 2 Yield & Quality5 Yield Equation Y = Prob ( zero defect on a chip ) = p (0) Y = ( 1 + Ad / ) Example: Ad = 1.0, α = 0.5, Y = 0.58 Unclustered defects: α = ∞, Y = e - Ad Example : Ad = 1.0, α = ∞, Y = 0.37 too pessimistic !

6
Copyright 2001, Agrawal & BushnellLecture 2 Yield & Quality6 Defect Level or Reject Ratio n Defect level (DL) is the ratio of faulty chips among the chips that pass tests. n DL is measured as parts per million (ppm). n DL is a measure of the effectiveness of tests. n DL is a quantitative measure of the manufactured product quality. For commercial VLSI chips a DL greater than 500 ppm is considered unacceptable.

7
Copyright 2001, Agrawal & BushnellLecture 2 Yield & Quality7 Determination of DL n From field return data: Chips failing in the field are returned to the manufacturer. The number of returned chips normalized to one million chips shipped is the DL. n From test data: Fault coverage of tests and chip fallout rate are analyzed. A modified yield model is fitted to the fallout data to estimate the DL.

8
Copyright 2001, Agrawal & BushnellLecture 2 Yield & Quality8 Modified Yield Equation n Three parameters: n Fault density, f = average number of stuck-at faults per unit chip area n Fault clustering parameter, β n Stuck-at fault coverage, T n The modified yield equation: Y (T ) = (1 + TAf / ) - Assuming that tests with 100% fault coverage (T =1.0) remove all faulty chips, Y = Y (1) = (1 + Af / ) -

9
Copyright 2001, Agrawal & BushnellLecture 2 Yield & Quality9 Defect Level Y (T ) - Y (1) DL (T ) = ——————— Y (T ) ( + TAf ) = 1 – —————— ( + Af ) Where T is the fault coverage of tests, Af is the average number of faults on the chip of area A, β is the fault clustering parameter. Af and β are determined by test data analysis.

10
Copyright 2001, Agrawal & BushnellLecture 2 Yield & Quality10 Example: SEMATECH Chip n Bus interface controller ASIC fabricated and tested at IBM, Burlington, Vermont n 116,000 equivalent (2-input NAND) gates n 304-pin package, 249 I/O n Clock: 40MHz, some parts 50MHz n 0.8m CMOS, 3.3V, 9.4mm x 8.8mm area n Full scan, 99.79% fault coverage n Advantest 3381 ATE, 18,466 chips tested at 2.5MHz test clock n Data obtained courtesy of Phil Nigh (IBM)

11
Copyright 2001, Agrawal & BushnellLecture 2 Yield & Quality11 Test Coverage from Fault Simulator Stuck-at fault coverage Vector number

12
Copyright 2001, Agrawal & BushnellLecture 2 Yield & Quality12 Measured Chip Fallout Vector number Measured chip fallout

13
Copyright 2001, Agrawal & BushnellLecture 2 Yield & Quality13 Model Fitting Y (T ) for Af = 2.1 and = 0.083 Measured chip fallout Y (1) = 0.7623 Chip fallout and computed 1 -Y (T ) Stuck-at fault coverage, T Chip fallout vs. fault coverage

14
Copyright 2001, Agrawal & BushnellLecture 2 Yield & Quality14 Computed DL Stuck-at fault coverage (%) Defect level in ppm 237,700 ppm (Y = 76.23%)

15
Copyright 2001, Agrawal & BushnellLecture 2 Yield & Quality15 Summary n VLSI yield depends on two process parameters, defect density (d ) and clustering parameter (α). n Yield drops as chip area increases; low yield means high cost. n Fault coverage measures the test quality. n Defect level (DL) or reject ratio is a measure of chip quality. n DL can be determined by an analysis of test data. n For high quality: DL < 500 ppm, fault coverage ~ 99%

16
Problems to Solve 1. Using the expression for defect level on Slide 9, derive test coverage (T) as a function of fault clustering parameter (β), defect level (DL), and average number of faults (Af) on a chip. 2. Find the defect level for: Fault density, f = 1.45 faults/sq. cm Fault clustering parameter, β = 0.11 Chip area = 1 cm 2 Fault Coverage, T = 95% Copyright 2001, Agrawal & BushnellLecture 2 Yield & Quality16

17
Solution 1 Copyright 2001, Agrawal & BushnellLecture 2 Yield & Quality17 Defect level, DL, is given on Slide 9, as follows: DL = 1 – [(β + Taf)/(β + Af)] β where T is the fault coverage, Af is the average number of faults on a chip of area A, and β is a fault clustering parameter. Further manipulation of this equation leads to the following result: (1 – DL) 1/β = (β + Taf)/(β + Af) or T = [{(β + Af)(1 – DL) 1/β – β}/(Af)] × 100 percent

18
Solution 2 Copyright 2001, Agrawal & BushnellLecture 2 Yield & Quality18 Defect level, DL, as given on Slide 9, is: DL(T) = 1 – [(β + Taf)/(β + Af)] β Substituting, Fault density, f = 1.45 faults/sq. cm Fault clustering parameter, β = 0.11 Chip area = 1 cm 2 Fault Coverage, T = 95% We get, DL(T) = 0.00522 or 5,220 parts per million

Similar presentations

OK

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 11 Lecture 1 Introduction n VLSI realization process n Verification and test n Ideal and real tests.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 11 Lecture 1 Introduction n VLSI realization process n Verification and test n Ideal and real tests.

© 2017 SlidePlayer.com Inc.

All rights reserved.

Ads by Google