1. Bounds on Defect Level and Fault Coverage in Linear Analog Circuit Testing Suraj Sindia (I.I.Sc, Bangalore) Virendra Singh (I.I.Sc, Bangalore) Vishwani D. Agrawal (Auburn University) VDAT 2009

2. Linear Circuits – Quick Recap Transfer function representation λ<µ 1

3. VDAT 2009 Circuit Parameters & Transfer Function Coefficients f 1 and f 2  Maps the parameter space & coefficient space.  Linear functions of circuit parameters  Can be potentially used to track the parametric drifts in circuit parameters Savir, ITC, 2002 R1R2C1C2R1R2C1C2 c1c2c1c2 Parameter SpaceCoefficient Space f1f1 f2f2 2

4. VDAT 2009 Background of TFC Method p2p2 p1p1 p3p3 c1c1 c2c2 c5c5 c4c4 c3c3 Coefficients as functions of circuit parameters 3

5. Closer Look at Coefficients x = p 1 (1-ρ)p 1n (1+ρ)p 1n (1+ρ*)p 1n (1-ρ*)p 1n p 2n p 1n y = p 2 ΛkΛk ΓkΓk ΞkΞk Legend Hypercube distribution of c k p 2n (1- ρ) p 2n (1+ ρ) Ω 4

6. VDAT 2009 Our Work – “Bounding” Defect Level:  Probability of a faulty chip escaping as a fault-free or a good chip Probability of a coefficient taking a value in the region Λ k Fault Coverage:  Percentage of faults that a given test method can uncover from set of all possible faults Probability of a coefficient taking a value in the region Γ k x = p 1 (1-ρ)p 1n (1+ρ)p 1n (1+ρ*)p 1n (1-ρ*)p 1n p 2n p 1n y = p 2 ΛkΛk ΓkΓk ΞkΞk Legend Hypercube distribution of c k p 2n (1- ρ) p 2n (1+ ρ) Ω 5

7. VDAT 2009 Our Work – “Bounding” Assume an appropriate p.d.f over the region of drift of p 1,p 2 Є [0,∞]  We choose Gaussian  Relevant for most of passive devices [R,L,C] Evaluate the joint Gaussian distribution over these regions Validate the bounds against number of components and coefficient of uncertainty(є) for common circuits –  Eg.: RC Ladder network 6

8. VDAT 2009 Equations – Two Parameter Case 7

9. VDAT 2009 Closed Form Expressions – N parameters Where, 8

10. VDAT 2009 Results – Plots of Expressions DL v/s number of circuit parameters DL v/s є 9

11. VDAT 2009 Simulated Plots for RC Ladder Defect Level 10

12. VDAT 2009 Simulated Plots for RC Ladder Fault Coverage 11

13. VDAT 2009 Simulation-Optimization Tradeoff Tradeoff point 12

14. VDAT 2009 Defect Level on Benchmarks Circuit Source Component Count Defect Level(%) Transistor Opamp Resistor Capacitor Total(N) Computed Simulated Operational ITC ’97a 8 -2 1 11 6.51 5.69 Amplifier #1 Con. Time State ITC ’97b -3 7 2 12 5.89 5.23 Variable filter Operational ITC ’97c 10 --1 11 6.51 5.69 Amplifier #2 Leapfrog Filter ITC ’97d -6 13 4 23 1.38 1.33 Digital-to-Analog ITC ’97e 16 1 17 1 35 0.21 0.2 Converter Differential Amplifier SFAa 4 -5 -9 7.72 6.43 Comparator SFAb -1 3 -4 7.78 3.75 Single Stage Amplifier SFAc 1 -5 -6 8.73 6.17 Elliptical filter SFAd -3 15 7 25 1.02 0.99 Low-Pass Filter Lucent1 -1 3 1 5 8.51 5.30 13

15. VDAT 2009 Fault Coverage on Benchmarks Circuit Source Component Count Fault Coverage(%) Transistor Opamp Resistor Capacitor Total(N) Computed Simulated Operational ITC ’97a 8 -2 1 11 84.78 85.31 Amplifier #1 Con. Time State ITC ’97b -3 7 2 12 87.17 87.66 Variable filter Operational ITC ’97c 10 --1 11 84.78 85.31 Amplifier #2 Leapfrog Filter ITC ’97d -6 13 4 23 98.05 98.19 Digital-to-Analog ITC ’97e 16 1 17 1 35 99.75 99.78 Converter Differential Amplifier SFAa 4 -5 -9 78.75 79.18 Comparator SFAb -1 3 -4 49.57 50.21 Single Stage Amplifier SFAc 1 -5 -6 64.19 64.87 Elliptical filter SFAd -3 15 7 25 98.61 98.72 Low-Pass Filter Lucent1 -1 3 1 5 57.50 58.18 14

16. VDAT 2009 Conclusion Closed form expressions for bounds on Defect Level and Fault Coverage in TFC based test of analog circuits Higher component count leads to  Smaller defect level  Better fault coverage Strategy for opting between simulation and non-linear optimization in TFC based test 15

17. Thanks for Your Attention!