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LAr40 Cold Electronics WBS 130.05.03.04 Craig Thorn 1Far Site Review, December 6-9, 2011.

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Presentation on theme: "LAr40 Cold Electronics WBS 130.05.03.04 Craig Thorn 1Far Site Review, December 6-9, 2011."— Presentation transcript:

1 LAr40 Cold Electronics WBS Craig Thorn 1Far Site Review, December 6-9, 2011

2 Outline  Scope & Requirements  Electronics specifications  Technical overview  Data rates  Zero-suppression  Electronics overview  Front-end (analog) ASIC  Digital (ADC, buffer, mux) ASIC  Cryogenic operation of CMOS ASICs  Electronics details and specifications  Schedule  Summary Far Site Review, December 6-9, Craig Thorn

3 Scope & Requirements  Scope: Can use WBS definitions (http://lbne2- docdb.fnal.gov:8080/cgi-bin/ShowDocument?docid=2163) for scope. Note that WBS#’s are out of date, also be sure text reflects current reference design choice.http://lbne2- docdb.fnal.gov:8080/cgi-bin/ShowDocument?docid=2163  Requirements: Get from Anne Heavey, DOORS output. (http://lbne2-docdb.fnal.gov:8080/cgi- bin/ShowDocument?docid=3747) Anne should have the outputs by Dec. 1 st.)http://lbne2-docdb.fnal.gov:8080/cgi- bin/ShowDocument?docid=3747 Far Site Review, December 6-9, Craig Thorn WBSNameWBS Dictionary Cold ElectronicsDetector electronics inside the cryostat including the front end preamp, shaper, ADC, MUX and optical driver. Most of these components are ASIC's. Also includes in-vessel circuit boards and interconnects. Includes design, procurement, fabrication and cold testing of all components and shipment to the underground site Cold electronics conceptual designCold electronics conceptual design Cold electronics preliminary designCold electronics preliminary design Cold electronics preliminary design review Cold electronics preliminary design review Cold electronics reliability testTest of long term reliability by operating a large number of front end boards near LAr temperature. This could be done in an existing LAr cryostat such as the membrane prototype if it is available, or it could be done in an existing or new LN cryostat Cold electronics final designCold electronics final design Cold electronics final design reviewCold electronics final design review Cold electronics constructionIncludes procurement, fabrication, assembly, cold testing and shipping to the APA assembly site.

4 Electronics Parameters ParameterValueUnitsReq IDNotes 90K563 electronsLAr-TPC-11BNL ASIC measured Electron lifetime assumption1.4 msLAr-TPC-11Set to achieve minimum S/N = 9 ADC sampling rate2 MHzLAr-TPC-11Same as ICARUS, MicroBooNE and ArgoNeuT Num MIP dynamic range15 LAr-TPC-1215 MIP ionization is a reasonable maximum value ADC resolution - min10 bitsLAr-TPC-11Minimum value required Readout redundancy4 Front end amplifier shaping time1.0 micro-sec Choices are 0.5, 1 and 2 micro-sec Analog front end power10 mW/chan Design goal Digital front end power5 mW/chan includes line driver power Far Site Review, December 6-9, Craig Thorn

5 White (Series) Noise: SNR Noise is 600 e rms MIP is e (1 attn length, 5 mm spacing) Threshold at 0.3 MIP: noise is 5 sigma (for these conditions 0.1% of points on a MIP track are lost) Probability of > 5 sigma is 2.8 x Read nearest neighbor wires + 2 leading & trailing samples Rate per APA is 3 x 5 x 2560 x 150 kHz x 12 x 2.8 x = 0.02 Mb/s Total Event Rate For Noise With Zero-suppression Total Event Rate For Noise With Zero-suppression Far Site Review, December 6-9, 2011 Craig Thorn 5

6 Ar 39 : Mean beta energy of 220 keV, endpoint 565 keV, 1.4 kBq/m 3 Kr 85 : Mean beta energy of 251 keV, endpoint 687 keV, 0.16 – 0.48 kBq/m 3 K 40, Co 60, Th 232, U 238 : in construction materials, gammas only, atten length <15 cm Ar spallation by cosmics: no cross section data, but not significant in WARP data Practical Maximum Data Rate of LAr20 Radioactive contaminants Practical Maximum Data Rate of LAr20 Radioactive contaminants The energy spectrum observed with the 2.3 liter WARP detector (Data) can be reproduced by 1.an internal component dominated by Ar 39 and Kr 85  emission inside the liquid argon. 2. an external component dominated by interactions of  -rays coming from U 238, Th 232, Co 60 and K 40 radioactivity of the materials surrounding the liquid argon P. Benetti et al., NIM A 574 (2007) 83 Craig Thorn 6Far Site Review, December 6-9, 2011

7 Practical Maximum Data Rate of LAr20 Radioactive contaminants Practical Maximum Data Rate of LAr20 Radioactive contaminants Ar 39 Decay rate is 122 kHz/APA Mean ionization is ~0.3 MIP 0.5 MIP, detected rate is 34 kHz Mean range of betas is 0.28 mm Read 3 wires and 10 samples Mean rate is 3 x 8 x 34,000 x 12 = 9.8 Mb/s Kr 85 Decay rate is ~28 kHz/APA Mean ionization is ~0.4 MIP 0.5 MIP, detected rate is 8 kHz Mean range of betas is 0.39 mm Read 3 wires and 5 samples Mean rate is 3 x 8 x 8,000 x 12 = 2.3 Mb/s Co 60 Only near SS APA frames since attenuation length is ~10 cm add ~0.2Mb/s (range of Compton electron is 1.3 cm) Calculation of 220 keV electrons in LAr from CASINO ex.html Far Site Review, December 6-9, 2011 Craig Thorn 7

8 Zero-suppression at FE reduces total volume of data to transmit Buffering on FE ASIC allows data to be transmitted at lower rate than sampling rate Readout rate must be high enough to avoid event “collisions” in one FE buffer With optimal zero-suppression, radioactivity, cosmics, and series FE noise give rates of 9.8 Mb/s for Ar 39 betas 2.3 Mb/s for Kr 85 betas 0.6 Mb/s for Co 60, Th & U gammas 0.02 Mb/s for FE series noise* 0.8 Mb/s for cosmic muons (1 Gb/s near surface**) Total is ~14 Mb/s (2 Gb) per APA at 800 (0) feet (cf. limit of 300Mb/s for copper, 3Gb/s for optical transmission per line) *For an enc of 600 RMS e -, a threshold at 3000 e - and 1 us shaping (zero-crossing rate of 150kHz). For a 1/e drift time of 2.4 ms, a drift of 3.7 m and a wire pitch of 5 mm, this threshold is 0.3 MIP. **Cosmic muon rate is 12 kHz (26 muon per drift, mean track length 2 m) Data Rates - Summary Far Site Review, December 6-9, 2011 Craig Thorn 8

9 Trigger derived from the logic OR of all collecting wires on an APA All channels on an APA continuously writing to the buffer until no signal from any collecting wire Baseline samples are compacted into smaller words (4bits) Not efficient: little data reduction Data volume is not sensitive to “noise” (thermal, induced, radioactivity, cosmics, …) 9 Far Site Review, December 6-9, 2011 Zero Suppression – APA Trigger Craig Thorn

10 Trigger derived from the logic OR of all channels in a chip All channels on a chip continuously writing to the buffer until no signal from any channel of a chip Baseline samples are compacted into smaller words (4bits) Data volume is sensitive to “noise” 10Far Site Review, December 6-9, 2011 Zero Suppression – Chip Trigger Craig Thorn

11 Trigger is derived from a single channel Write enable is applied to the i, i+1, and i-1 wires to cover any shared, below threshold signals Read ahead and after the write enable gate to capture the below threshold leading/trailing edges of a waveform Minimum data volume Data volume is less sensitive to “noise” 11Far Site Review, December 6-9, 2011 Zero Suppression – Channel Trigger Craig Thorn

12 FEE Design Guidelines & Constraints some factors relevant to the design of final in-LAr readout architecture reliability lifetime dead timenumber of feed-throughs power dissipation flexibility back-end redundancy low multiplexing, low clock frequency ↕ (conflict) high multiplexing, high clock frequency token-passing (design option) programmability (design, operation) compression sparsification neighboring smart threshold derandomization (deep memory) zero suppression 12Far Site Review, December 6-9, 2011 Craig Thorn

13 LAr TPC - Cold CMOS Electronics Block Diagram – Lar40 Reference Design LAr TPC - Cold CMOS Electronics Block Diagram – Lar40 Reference Design Far Site Review, December 6-9, Craig Thorn

14 LAr TPC - Cold CMOS Electronics Block Diagram – LAr40 Alternate Design LAr TPC - Cold CMOS Electronics Block Diagram – LAr40 Alternate Design Far Site Review, December 6-9, Craig Thorn

15 16 channels charge amplifier (adj. gain) high-order filter (adj. time constant) ac/dc, adjustable baseline test capacitor, channel mask ADC (12-bit, 2 MS/s) compression, discrimination multiplexing and digital buffering LV or CM digital interface pulse generator, analog monitor temperature sensor LAr environment (> 20 years at 88K) estimated total size ~ 6 x 8 mm² estimated power ~ 10 mW/channel LAr TPC Front-End ASIC

16 16 channels charge amplifier, h igh-order filter adjustable gain: 4.7, 7.8, 14, 25 mV/fC (charge 55, 100, 180, 300 fC) adjustable filter time constant (peaking time 0.5, 1, 2, 3 µs) selectable collection/non-collection mode (baseline 200, 800 mV) selectable dc/ac coupling (100µs) rail-to-rail analog signal processing band-gap referenced biasing temperature sensor (~ 3mV/°C) 136 registers with digital interface 5.5 mW/channel (input MOSFET 3.9 mW) single MOSFET test structures ~ 15,000 MOSFETs designed for room (300K) and cryogenic (77K) operation technology CMOS 0.18 µm, 1.8 V Analog ASIC Far Site Review, December 6-9, Craig Thorn

17 Adjustable gain, peaking time and baseline maximum charge 55, 100, 180, 300 fC Pole-zero cancellation at 77K to be addressed in next revision Bandgap Reference variation ≈ 1.8 % Temperature Sensor ~ 2.86 mV / °K Signal Measurements Far Site Review, December 6-9,

18 Far Site Review, December 6-9, 2011 Noise ~ 250e - w/o C det w. t p =1 μ Crosstalk < 0.7% Noise < 1000e - w. C det =150pF & t p =1 μ RT Analog ASIC - Signal Measurements Warm tests for MicroBooNE 18

19 Far Site Review, December 6-9, 2011 FEE ASIC Evaluation Noise, Gain, and Shaping Time FEE ASIC Evaluation Noise, Gain, and Shaping Time 19

20 Measurements affected by: input line parasitic resistance ~ 150 e - at 77 K (~ 590 e - at 300K ) addressed in next revision Layout Detail Input MOSFET L = 270 nm W = 10 mm (50µm x 200) g m,77K ≈ 90 mS (11 Ω ) g m,300K ≈ 45 mS (22 Ω ) Input Line L ≈ 1 mm W = 3.5 µm (M3 + M4) R 77K ≈ 3 Ω R 300K ≈ 12 Ω C IN dielectric noise (not present in wire) ~ 60 e - at 77 K Analog ASIC - Noise Measurements ASIC version #3 designed and fabricated, currently being tested Dynamic Range > 3,000 Q max =300fC 20

21 Issues Addressed in Version 2 Analog front-end input MOSFET optimization → MOSFET width doubled noise from resistance of input lines → line width doubled Start-up failures in some bias circuit → start-up circuits added (due to new BGR biasing circuits) 21 Craig Thorn

22 Residual Issues in Version 2 CMP damage in AC/DC circuit (found in a few samples) Some packaging issues DC PSR can be improved no baseline stabilization possible, due to constraint on measurement time 22Far Site Review, December 6-9, 2011 Craig Thorn

23 to buffer (metal 6) from filter switch metal 5 interconnect line Capacitor Resistor 1,100µm 280µm Only possible explanation: high series resistance (up to open) DC AC metal 6 metal 5 risk of CMP damage CMP Damage 23

24 Damage due to discharge from Chemical-Mechanical Polishing (CMP) during fabrication DC good channel good channel damaged channel damage d channel CMP Damage 24 Far Site Review, December 6-9, 2011 Craig Thorn

25 LArASIC3 sent for fabrication on July 25 th Received and under evaluation LArASIC2 LArASIC3 size 6010 x 5707 µm² FE ASIC Version 3 bias circuit for high PSR 25Far Site Review, December 6-9, 2011 Craig Thorn

26 Current mode ADC dual stage 6-MSBs in 150ns, 6-LSBs in 250ns single trigger conversion per stage 12-bit resolution 2 MS/s conversion rate power dissipation 3.6 mW at 2 MS/s power-down option for low rate applications wake up in few tens of ns layout size: 0.23 mm x 1.25 mm ADC cell Clockless low power ADC stage Demonstrated in ASIC for SNS, see De Geronimo, et al., IEEE Trans NSS, 54 (2007) 541 ADC - Architecture Far Site Review, December 6-9, Craig Thorn

27 operation verified at room and cryogenic temperatures differential non-linearity limited by timing design error in control circuit integral non-linearity limited by mismatch (linear → common centroid) ADC - Preliminary Results ASIC revision designed and fabricated; under evaluation ADC output - 500mV dc σ =1.1LSB 77 K ADC output V sine 300 K 16-channel ADC+buffer 6mm 4.3 mm 27 Craig Thorn

28 Schedule (install by others)  Schedule provided by Ken Far Site Review, December 6-9, FY10FY11FY12FY13FY14FY15FY16FY17FY18FY19FY20FY21FY22 CD-0: 1/2010 Beneficial Occupancy: 10/2018 CD-1: 6/2012 CD-2: 9/2013 CD-3: 12/2014 Designs Construction Checkout Craig Thorn

29 Milestones Far Site Review, December 6-9, Craig Thorn

30 Summary Far Site Review, December 6-9, Craig Thorn CMOS performs better at cryogenic temperatures Defined and predictable design for cryogenic T is possible Low-noise at cryogenic T demonstrated ENC < 1,000 e - at 200pF ~5mW/ch. characterization and modeling of CMOS 180nm Long lifetime at cryogenic T possible with guidelines Critical building blocks - front-end & ADC - developed Future work Improve cryogenic static models Optimize ADC Merge, add zero-suppression & buffering, and finalize

31 Backup Information Far Site Review, December 6-9,

32 two independent 8-channel sections ( a and b ) ADC max 2MS/s, 12-bit, calibrated for zero at baseline mem can store one full-depth event (3K) per channel 8x analog 8x AD C thr/ trig cmp mem 3K mux 8:1 8x analog 8x AD C thr/ trig cmp mem 3K mux 8:1 bias, pulser, logic, registers ae re ck flg w i wowo d b t ba, t bb d a t aa, t ab section a section b ASIC Architecture d a, d b = data out t aa, t ab, t ba, t bb = triggers in/out ( edge channels ) ae = acquisition enable (sync/reset acquisition at positive edge) re = readout enable ck = clock 32 or 64 MHz rck (readout clock) 32 or 64 MHz tck (timestamp & ADC clock) 2MHz cck (test pulse clock) 8 kHz wck (write clock) 8 MHz flg = flag ( full indicator, stops acquisition, restarts at 3/4 buffer empty ) w i, w o = configuration in/out event stored in mem if: (i) above threshold or (ii) external trigger from neighbor (or FPGA) 32

33 0 (16)amplitude datatime1 (10)addr (12)1 (16) max block size 4096-bit variable block length, max 4096 bit startend id (4) Data Format block-start: 16 ones block-end: 16 zeros address 12-bit 5-bit hard-assigned + 7-bit soft-assigned all 0 and all 1 not allowed timestamp 20-bit (2 x 10-bit) associated to threshold crossing Gray-code, 500 ns (2 MHz), ~500 ms full scale all 0 and all 1 not allowed block id (same timestamp) 4-bit resets at each new timestamp all 0 and all 1 not allowed amplitude data 14-bit or n-bit compress if below compression-threshold (programmable) first bit: compression id (0 = compressed data, 1 = full data) second bit: polarity (0 = negative, 1 = positive) next bits: amplitude (12 for uncompressed, n-2 for compressed) max amplitude length = 4028 bit (~288x14-bit) can be broken to next block as needed all 0 and all 1 not allowed time2 (10) 33 Craig Thorn

34 Cost Estimate Far Site Review, December 6-9, Craig Thorn

35 Labor vs M&S Far Site Review, December 6-9, Craig Thorn


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