1. Nanoelectromechanical Switches
(NEM Relays & NEMFETs)
Dimitrios Tsamados
Adrian Ionescu
EPFL
Kerem Akarvardar
H.-S. Philip Wong
Stanford
Elad Alon
Tsu-Jae King Liu
UC Berkeley

2. Outline
Part I: NEM Relays
Motivation
Device operation
Logic gate configurations
State-of-the-art
Scaling and performance
Issues
Conclusion
Part II: NEMFETs

3. Motivation Motivation
Two key properties unavailable in CMOS
Infinite subthreshold slope
Zero Leakage
Ultra-low VDD
without degrading Ion
Zero static energy
Ultra-low dynamic energy
Ultra-low energy operation beyond the capability of CMOS

4. (Case Western Reserve U.)
Extra Motivation
Motivation
Hysteresis
Stiction
Low temperature process
High temperature operation
High radiation hardness
Cheap substrates
SRAM and NV Memory
Choi et al. IEDM 2007
(UC Berkeley)
3-D integration and
hybrid NEMS/CMOS
Chakraborty et al.
IEEE Trans. Circ. Syst. 2007
(Case Western Reserve U.)
Niche applications
Reduced cost

5. Conventional Device Structure & Operation
Operation of the NEM Relay
Conventional Device Structure & Operation
limit stop 1
cantilever beam
air gap
Normalized Position S G D
insulating substrate
VGS
OFF-state
infinite slope
Drain Current
zero leakage S G D
VGS
Pull-out voltage, Vpo
Pull-in voltage, Vpi
= VDD,min
ON-state

6. Logic Implementation and Interconnection
Operation of the NEM Relay S D
VDD S D G G
laterally-actuated cantilever
MOSFET
NEM RELAY
VDD
VDD in
out
"p-type"
laterally-actuated cantilever
"n-type"
top view
Lee et al. SPIE 2005
(Simon Fraser U. – Canada)
GND
CMOS
CNEM
CMOS schematics can be used in CNEM logic circuits
No conductivity difference between the n-type and p-type relays
Simple layout enabling to small area

7. Energy-Reversible (ER) CNEM Logic Gates
Operation of the NEM Relay
Laterally-actuated ER CNEM Inverter
Elastic potential energy, which is stored due to beam bending, is reversibly used for switching
Akarvardar et al. DRC 2008
ER principle: Yang et al. MME 2003
Delft University – The Netherlands
Top View

8. Energy-Reversible CNEM Logic Gates
Operation of the NEM Relay
Energy-Reversible CNEM Logic Gates
Normalized Position V GS 1 pi po
(energy -
reversible)
(conventional)
VDD,min
Conventional
energy-reversible
Pakula et al. (Delft U.) IEEE Sensors 2005
Reduced VDD & dynamic energy
(unless hysteresis is prevented)
Experimentally demonstrated in RF
switches (VDD = 5 V instead of Vpi = 38 V)
Any logic function can be realized
ER Relays: ER
NAND
Gate

9. (KAIST & Samsung – Korea)
State-of-the-Art
The smallest 2-terminal switch ever reported:
Jang et al. APL 92, 2008
(KAIST & Samsung – Korea)
300 nm
Vpo = 8 V
Vpi = 13 V
15 nm gap
35 nm beam thickness
TiN beam, sacrificial poly-Si,
wet etch + critical point dry
Several hundred cycles
endurance (insulator failure)
zero leakage
infinite slope

10. Hayamizu et al. Nature Nanotech 3
State-of-the-Art
Self-assembled "CNT wafers" on pre-patterned substrates
Hayamizu et al. Nature Nanotech 3
2008 (AIST – Japan)
>1250
relays
Parallel, scalable, and reproducible relay fabrication with > 95% structural yield
~5000 SWNTs

11. Constant-Field Scaling Constant-Field Scaling
Scaling => smaller and faster relay that dissipates less energy
vdW Forces tend to become dominant at nanoscale

12. stiffer beams to compensate for Fvdw
Performance
L = 250 nm
scaling
silicon
4 nm
Fvdw ↑
delay ↓
~ 1 ns
stiffer beams to compensate for Fvdw
1 ns switching delay
1.5 V supply voltage
80 aJ switching energy
0.03 μm2 lateral inverter area
=> competitive with CMOS
Zero leakage
increased VDD
~ 1 V
Negligible Fvdw =>
1 VDD  150 mV
Akarvardar et al. IEDM 2007

13. NEM relays vs. Low-Power CMOS
Lg = 45 nm LSTP CMOS (ITRS):
High VT (0.53 V) => Very low leakage (30 pA/μm)
Zero leakage advantage of the NEM relay would only be apparent in logic circuits with relatively high device count and low activity
CV/I = 1 VDD = 425 mV
NEM relays should achieve nanosecond-range intrinsic VDD << 425 mV
=> Decrease the vdw forces substantially
How?
=> And/or operate close to the stiction limit
Increased sensitivity to device param.
Akarvardar et al. submitted to IEDM 2008

14. Issues Contact reliability hot switching high current density
high impact velocity
2. Sticking: limits the voltage scaling
3. Packaging: hermetic sealing is required
4. Tunneling: determines the minimum gap
5. Long settling time & tip bouncing: tend to
increase the switching delay
6. Brownian motion: leads to switching errors

15. Conclusion
NEM logic can become an alternative ultra-low power logic technology if:
Contacts can be reliably implemented at nanoscale
Nanosecond range delays can be achieved at a
few 100 mV
Detailed roadmapping and intensive engineering development are recommended

16. Nano-Electro-Mechanical FETs

17. Hybrid M/NEMS Hybrid M/NEM devices: Pure M/NEM devices:
micro/nano movable parts
solid state semiconductor device involved in operation
Pure M/NEM devices:
micro/nano movable parts
passive device operation
Ex: suspended nano-beams
Ex: suspended-gate FETs
Drain
Gate
Source

18. M/NEM-FET: device architectures
Out-of-plane
In-plane
Move gate
Move body
Major advantages: new functionality and low power

19. M/NEM-FET abrupt switch
Experiment:
Out-of-plane movable gate
Resonant-Gate FET (Nathanson, 1966)
Suspended-Gate MOSFET (EPFL: A.M. Ionescu, ISQED 2001, IEDM 2005, 2006)
Nano-electro-mechanical FET (UC Berkeley, T.J. King, IEDM 2005)
Modeling of SG-FET (Stanford & EPFL: Akarvardar: IEEE TED 2008, Tsamados: SSE 2008)
Gate down
low Vt
Cox
movable
gate
Gate up:
high Vt
in-series Cgap
Applications: power management, low power logic, memory

20. NEMS simulation & modeling
Electrostatic NEMS: mechanical & electrostatic analysis
Source: G. Li et al, Urbana-Champaign.

21. NEM-FET: scaling & simulation
Multi-physics simulation for hybrid NEM device design
Coupled FEA: 2D ANSYS-DESSIS for suspended-gate FET
Simulation: 90nm NEM-FET

22. NEM-FET power management switch
NEM-FET vs. MOSFET power management switch:
dynamic VT
Ioff, Isubthreshold :
sleep area ~ MOSFET
Replaced by NEM-FET

23. Hysteresis: 1T MEM-FET memory
Drain
Gate
Source
N. Abelé et al., IEDM 2006
Electro-mechanical hysteresis: [ Vpull-in – Vpull-out ]
SG-MOSFET capacitor-less memory feasible
Hysteresis control! Scaling? Reliability?

24. Size & Voltage operation scaling (1)
nanogap scaling (Samsung)
tbeam= 20nm
tgap = 20nm
NEM clamp switch with TiN beam memory cell array structure for high density non-volatile memory application
M.-S. Kim et al., ISDRS 2007

25. Size & Voltage operation scaling (2)
VD=1.2V
SG-FET compliant to ITRS 90nm node:
tox=2nm, L=65nm, channel doping Nch=3×1018cm−3, μ0=278cm2/Vs , air-gap g0=5nm, W=400nm, h=10nm, Young modulus, E=170GPa.

26. NEM-FET inverter
significant power savings (1-2 decades reduction) of inverter peak current
no leakage power compared with nano-meter scaled CMOS inverter.

27. Movable/vibrating gate transistor
Laterally (in-plane) vibrating gate
lateral MOS transistor, detection in drain current
+4.3dB experimental gain demonstrated compared to capacitive detection using same structure
LETI-CEA
e-beam defines gaps (~47nm gap resol.).
L=10mm, W=165nm, d=120nm
C. Durand et al., IEEE EDL 2008.

28. Double Gate switchable/vibrating body FET
fres=2.4MHz, Q=6’000, Rm=200Ohm
Laterally (in-plane) movable body:
first demonstration of +30dB signal improvement
EPFL
D. Grogg, A.M. Ionescu, DRC 2008.

29. Double Gate switchable/vibrating body FET
Experiment
D. Grogg, A.M. Ionescu,
ESSDERC 2008, Confidential

30. Conclusion
NEM-FET: true hybrid mechanical-solid-state switch with near-zero point subthreshold swing
attractive for low-Ioff power management switches, capacitor-less memory (D-RAM, S-RAM and NVM with appropriate storage layers) and new analog/RF functionality (in the resonant-gate configuration).
fabrication: compatibility of surface micromachining with CMOS processing.
Voltage scaling below 1-2V: nanogap technology
Size: ~as scalable as MOSFET (anchors needed)
NEMFET does not use mechanical contacts in the path of current flow: long-term reliability comparable to that of capacitive RF MEMS switches (>109 cycles), being limited by oxide charging.

31. MEMS/NEMS application roadmap
NEM sensing

32. MEMS/NEMS application roadmap
NEMS àBeyond CMOS = low power nano-switch
àMore than Moore = new functionality
Key role of NEMS for power savings and new functionality: future hybrid NEMS-CMOS
Future role of true hybrid NEM-FET devices:
abrupt switch, memory, resonator, sensing
Challenges for hybrid NEM-FET:
additional process control of nanoscale air-gap, thickness and uniformity of suspended structures, control and uniformity of mechanical properties
fabrication: top-down & bottom-up (Si, CNTs)
wafer-level packaging and reliability
thermal drift

33. Acknowledgments EPFL: FP7 IST projects MIMOSA, MINAMI and NANO-RF
Stanford: DARPA, FCRP C2S2, NSF
Roger T. Howe, David Elata,
J Provine, Roozbeh Parsa,
Kyeongran Yoo, Soogine Chong
UC Berkeley: DARPA, FCRP C2S2
Hei Kam