Presentation on theme: "Nanoelectromechanical Switches"— Presentation transcript:
1 Nanoelectromechanical Switches (NEM Relays & NEMFETs)Dimitrios TsamadosAdrian IonescuEPFLKerem AkarvardarH.-S. Philip WongStanfordElad AlonTsu-Jae King LiuUC Berkeley
2 OutlinePart I: NEM RelaysMotivationDevice operationLogic gate configurationsState-of-the-artScaling and performanceIssuesConclusionPart II: NEMFETs
3 Motivation Motivation Two key properties unavailable in CMOSInfinite subthreshold slopeZero LeakageUltra-low VDDwithout degrading IonZero static energyUltra-low dynamic energyUltra-low energy operation beyond the capability of CMOS
4 (Case Western Reserve U.) Extra MotivationMotivationHysteresisStictionLow temperature processHigh temperature operationHigh radiation hardnessCheap substratesSRAM and NV MemoryChoi et al. IEDM 2007(UC Berkeley)3-D integration andhybrid NEMS/CMOSChakraborty et al.IEEE Trans. Circ. Syst. 2007(Case Western Reserve U.)Niche applicationsReduced cost
5 Conventional Device Structure & Operation Operation of the NEM RelayConventional Device Structure & Operationlimit stop1cantilever beamair gapNormalized PositionSGDinsulating substrateVGSOFF-stateinfinite slopeDrain Currentzero leakageSGDVGSPull-out voltage, VpoPull-in voltage, Vpi= VDD,minON-state
6 Logic Implementation and Interconnection Operation of the NEM RelaySDVDDSDGGlaterally-actuated cantileverMOSFETNEM RELAYVDDVDDinout"p-type"laterally-actuated cantilever"n-type"top viewLee et al. SPIE 2005(Simon Fraser U. – Canada)GNDCMOSCNEMCMOS schematics can be used in CNEM logic circuitsNo conductivity difference between the n-type and p-type relaysSimple layout enabling to small area
7 Energy-Reversible (ER) CNEM Logic Gates Operation of the NEM RelayLaterally-actuated ER CNEM InverterElastic potential energy, which is stored due to beam bending, is reversibly used for switchingAkarvardar et al. DRC 2008ER principle: Yang et al. MME 2003Delft University – The NetherlandsTop View
8 Energy-Reversible CNEM Logic Gates Operation of the NEM RelayEnergy-Reversible CNEM Logic GatesNormalized PositionVGS1pipo(energy-reversible)(conventional)VDD,minConventionalenergy-reversiblePakula et al. (Delft U.) IEEE Sensors 2005Reduced VDD & dynamic energy(unless hysteresis is prevented)Experimentally demonstrated in RFswitches (VDD = 5 V instead of Vpi = 38 V)Any logic function can be realizedER Relays:ERNANDGate
10 Hayamizu et al. Nature Nanotech 3 State-of-the-ArtSelf-assembled "CNT wafers" on pre-patterned substratesHayamizu et al. Nature Nanotech 32008 (AIST – Japan)>1250relaysParallel, scalable, and reproducible relay fabrication with > 95% structural yield~5000 SWNTs
11 Constant-Field Scaling Constant-Field Scaling Scaling => smaller and faster relay that dissipates less energyvdW Forces tend to become dominant at nanoscale
12 stiffer beams to compensate for Fvdw PerformanceL = 250 nmscalingsilicon4 nmFvdw ↑delay ↓~ 1 nsstiffer beams to compensate for Fvdw1 ns switching delay1.5 V supply voltage80 aJ switching energy0.03 μm2 lateral inverter area=> competitive with CMOSZero leakageincreased VDD~ 1 VNegligible Fvdw =>1 VDD 150 mVAkarvardar et al. IEDM 2007
13 NEM relays vs. Low-Power CMOS Lg = 45 nm LSTP CMOS (ITRS):High VT (0.53 V) => Very low leakage (30 pA/μm)Zero leakage advantage of the NEM relay would only be apparent in logic circuits with relatively high device count and low activityCV/I = 1 VDD = 425 mVNEM relays should achieve nanosecond-range intrinsic VDD << 425 mV=> Decrease the vdw forces substantiallyHow?=> And/or operate close to the stiction limitIncreased sensitivity to device param.Akarvardar et al. submitted to IEDM 2008
14 Issues Contact reliability hot switching high current density high impact velocity2. Sticking: limits the voltage scaling3. Packaging: hermetic sealing is required4. Tunneling: determines the minimum gap5. Long settling time & tip bouncing: tend toincrease the switching delay6. Brownian motion: leads to switching errors
15 ConclusionNEM logic can become an alternative ultra-low power logic technology if:Contacts can be reliably implemented at nanoscaleNanosecond range delays can be achieved at afew 100 mVDetailed roadmapping and intensive engineering development are recommended
24 Size & Voltage operation scaling (1) nanogap scaling (Samsung)tbeam= 20nmtgap = 20nmNEM clamp switch with TiN beam memory cell array structure for high density non-volatile memory applicationM.-S. Kim et al., ISDRS 2007
25 Size & Voltage operation scaling (2) VD=1.2VSG-FET compliant to ITRS 90nm node:tox=2nm, L=65nm, channel doping Nch=3×1018cm−3, μ0=278cm2/Vs , air-gap g0=5nm, W=400nm, h=10nm, Young modulus, E=170GPa.
26 NEM-FET invertersignificant power savings (1-2 decades reduction) of inverter peak currentno leakage power compared with nano-meter scaled CMOS inverter.
27 Movable/vibrating gate transistor Laterally (in-plane) vibrating gatelateral MOS transistor, detection in drain current+4.3dB experimental gain demonstrated compared to capacitive detection using same structureLETI-CEAe-beam defines gaps (~47nm gap resol.).L=10mm, W=165nm, d=120nmC. Durand et al., IEEE EDL 2008.
28 Double Gate switchable/vibrating body FET fres=2.4MHz, Q=6’000, Rm=200OhmLaterally (in-plane) movable body:first demonstration of +30dB signal improvementEPFLD. Grogg, A.M. Ionescu, DRC 2008.
29 Double Gate switchable/vibrating body FET ExperimentD. Grogg, A.M. Ionescu,ESSDERC 2008, Confidential
30 ConclusionNEM-FET: true hybrid mechanical-solid-state switch with near-zero point subthreshold swingattractive for low-Ioff power management switches, capacitor-less memory (D-RAM, S-RAM and NVM with appropriate storage layers) and new analog/RF functionality (in the resonant-gate configuration).fabrication: compatibility of surface micromachining with CMOS processing.Voltage scaling below 1-2V: nanogap technologySize: ~as scalable as MOSFET (anchors needed)NEMFET does not use mechanical contacts in the path of current flow: long-term reliability comparable to that of capacitive RF MEMS switches (>109 cycles), being limited by oxide charging.
32 MEMS/NEMS application roadmap NEMS àBeyond CMOS = low power nano-switchàMore than Moore = new functionalityKey role of NEMS for power savings and new functionality: future hybrid NEMS-CMOSFuture role of true hybrid NEM-FET devices:abrupt switch, memory, resonator, sensingChallenges for hybrid NEM-FET:additional process control of nanoscale air-gap, thickness and uniformity of suspended structures, control and uniformity of mechanical propertiesfabrication: top-down & bottom-up (Si, CNTs)wafer-level packaging and reliabilitythermal drift
33 Acknowledgments EPFL: FP7 IST projects MIMOSA, MINAMI and NANO-RF Stanford: DARPA, FCRP C2S2, NSFRoger T. Howe, David Elata,J Provine, Roozbeh Parsa,Kyeongran Yoo, Soogine ChongUC Berkeley: DARPA, FCRP C2S2Hei Kam