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Nanoelectromechanical Switches (NEM Relays & NEMFETs) Dimitrios Tsamados Adrian Ionescu EPFL Kerem Akarvardar H.-S. Philip Wong Stanford Elad Alon Tsu-Jae.

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Presentation on theme: "Nanoelectromechanical Switches (NEM Relays & NEMFETs) Dimitrios Tsamados Adrian Ionescu EPFL Kerem Akarvardar H.-S. Philip Wong Stanford Elad Alon Tsu-Jae."— Presentation transcript:

1 Nanoelectromechanical Switches (NEM Relays & NEMFETs) Dimitrios Tsamados Adrian Ionescu EPFL Kerem Akarvardar H.-S. Philip Wong Stanford Elad Alon Tsu-Jae King Liu UC Berkeley

2 2 Outline Motivation Device operation Logic gate configurations State-of-the-art Scaling and performance Issues Conclusion Part I: NEM Relays Part II: NEMFETs

3 3 Motivation Two key properties unavailable in CMOS Zero Leakage Zero static energy Infinite subthreshold slope Ultra-low V DD without degrading I on Ultra-low dynamic energy Ultra-low energy operation beyond the capability of CMOS

4 4 Motivation Extra Motivation Hysteresis Stiction Low temperature process High temperature operation High radiation hardness Cheap substrates SRAM and NV Memory 3-D integration and hybrid NEMS/CMOS Niche applications Reduced cost Choi et al. IEDM 2007 (UC Berkeley) Chakraborty et al. IEEE Trans. Circ. Syst (Case Western Reserve U.)

5 5 Operation of the NEM Relay OFF-state S G D ON-state Pull-in voltage, V pi = V DD,min Pull-out voltage, V po Normalized Position V GS 1 0 Drain Current V GS S D G insulating substrate air gap limit stop cantilever beam Conventional Device Structure & Operation infinite slope zero leakage

6 6 Operation of the NEM Relay Logic Implementation and Interconnection CMOS schematics can be used in CNEM logic circuits No conductivity difference between the n-type and p-type relays Simple layout enabling to small area MOSFET NEM RELAY CMOS CNEM S D G SD G V DD in out V DD GND laterally- actuated cantilever Lee et al. SPIE 2005 (Simon Fraser U. – Canada) "n-type" "p-type" top view

7 7 Operation of the NEM Relay Energy-Reversible (ER) CNEM Logic Gates Top View Laterally-actuated ER CNEM Inverter Elastic potential energy, which is stored due to beam bending, is reversibly used for switching Akarvardar et al. DRC 2008 ER principle: Yang et al. MME 2003 Delft University – The Netherlands

8 8 Operation of the NEM Relay Energy-Reversible CNEM Logic Gates Conventional energy- reversible ER NAND Gate Pakula et al. (Delft U.) IEEE Sensors 2005 Reduced V DD & dynamic energy (unless hysteresis is prevented) Experimentally demonstrated in RF switches (V DD = 5 V instead of V pi = 38 V) Any logic function can be realized ER Relays: Normalized Position V GS 1 0 V pi V po 0 (energy-reversible) (conventional) V DD,min

9 9 State-of-the-Art The smallest 2-terminal switch ever reported: Jang et al. APL 92, 2008 (KAIST & Samsung – Korea) 15 nm gap 35 nm beam thickness TiN beam, sacrificial poly-Si, wet etch + critical point dry Several hundred cycles endurance (insulator failure) zero leakage infinite slope V po = 8 V V pi = 13 V 300 nm

10 10 State-of-the-Art Hayamizu et al. Nature Nanotech (AIST – Japan) Self-assembled "CNT wafers" on pre-patterned substrates ~5000 SWNTs Parallel, scalable, and reproducible relay fabrication with > 95% structural yield >1250 relays

11 11 Scaling => smaller and faster relay that dissipates less energy vdW Forces tend to become dominant at nanoscale Constant-Field Scaling

12 12 Performance Akarvardar et al. IEDM ns switching delay 1.5 V supply voltage 80 aJ switching energy 0.03 μm 2 lateral inverter area => competitive with CMOS Zero leakage L = 250 nm silicon scaling delay ↓ F vdw ↑ stiffer beams to compensate for F vdw increased V DD ~ 1 ns ~ 1 V Negligible F vdw => 1 V DD  150 mV 4 nm

13 13 NEM relays vs. Low-Power CMOS L g = 45 nm LSTP CMOS (ITRS): NEM relays should achieve nanosecond-range intrinsic V DD << 425 mV => Decrease the vdw forces substantially How? => And/or operate close to the stiction limit Increased sensitivity to device param. Akarvardar et al. submitted to IEDM 2008 CV/I = 1 V DD = 425 mV Zero leakage advantage of the NEM relay would only be apparent in logic circuits with relatively high device count and low activity High V T (0.53 V) => Very low leakage (30 pA/μm)

14 14 Issues 1. Contact reliability hot switching high current density high impact velocity 2. Sticking: limits the voltage scaling 3. Packaging: hermetic sealing is required 4. Tunneling: determines the minimum gap 5. Long settling time & tip bouncing: tend to increase the switching delay 6. Brownian motion: leads to switching errors

15 15 Conclusion NEM logic can become an alternative ultra-low power logic technology if: Contacts can be reliably implemented at nanoscale Nanosecond range delays can be achieved at a few 100 mV Detailed roadmapping and intensive engineering development are recommended

16 Nano-Electro-Mechanical FETs

17 17 Hybrid M/NEMS Pure M/NEM devices: - micro/nano movable parts - passive device operation Hybrid M/NEM devices: - micro/nano movable parts - solid state semiconductor device involved in operation Drain Source Gate Ex: suspended nano-beamsEx: suspended-gate FETs

18 18 M/NEM-FET: device architectures Out-of-plane In-plane Move gate Move body Major advantages: new functionality and low power

19 19 Resonant-Gate FET (Nathanson, 1966) Suspended-Gate MOSFET (EPFL: A.M. Ionescu, ISQED 2001, IEDM 2005, 2006) Nano-electro-mechanical FET (UC Berkeley, T.J. King, IEDM 2005) Modeling of SG-FET (Stanford & EPFL: Akarvardar: IEEE TED 2008, Tsamados: SSE 2008) movable gate Experiment: Out-of-plane movable gate Gate up: high V t in-series C gap Gate down low V t C ox Applications: power management, low power logic, memory M/NEM-FET abrupt switch

20 20 NEMS simulation & modeling Electrostatic NEMS: mechanical & electrostatic analysis Source: G. Li et al, Urbana-Champaign.

21 21 Simulation: 90nm NEM-FET NEM-FET: scaling & simulation Multi-physics simulation for hybrid NEM device design Coupled FEA: 2D ANSYS-DESSIS for suspended-gate FET

22 22 NEM-FET vs. MOSFET power management switch: dynamic V T I off, I subthreshold : sleep area ~ MOSFET Replaced by NEM-FET NEM-FET power management switch

23 Drain Source Gate Electro-mechanical hysteresis: [ V pull-in – V pull-out ] SG-MOSFET capacitor-less memory feasible Hysteresis control! Scaling? Reliability? N. Abelé et al., IEDM 2006 Hysteresis: 1T MEM-FET memory

24 24 Size & Voltage operation scaling (1) nanogap scaling (Samsung) t beam = 20nm t gap = 20nm NEM clamp switch with TiN beam memory cell array structure for high density non-volatile memory application M.-S. Kim et al., ISDRS 2007

25 25 SG-FET compliant to ITRS 90nm node: tox=2nm, L=65nm, channel doping Nch=3×10 18 cm −3, μ0=278cm 2 /Vs, air- gap g0=5nm, W=400nm, h=10nm, Young modulus, E=170GPa. V D =1.2V Size & Voltage operation scaling (2)

26 26 significant power savings (1-2 decades reduction) of inverter peak current no leakage power compared with nano- meter scaled CMOS inverter. NEM-FET inverter

27 27 Movable/vibrating gate transistor Laterally (in-plane) vibrating gate lateral MOS transistor, detection in drain current +4.3dB experimental gain demonstrated compared to capacitive detection using same structure C. Durand et al., IEEE EDL e-beam defines gaps (~47nm gap resol.). L=10  m, W=165nm, d=120nm LETI-CEA

28 28 D. Grogg, A.M. Ionescu, DRC Laterally (in-plane) movable body: first demonstration of +30dB signal improvement Double Gate switchable/vibrating body FET EPFL f res =2.4MHz, Q=6’000, R m =200Ohm

29 29 D. Grogg, A.M. Ionescu, ESSDERC 2008, Confidential Double Gate switchable/vibrating body FET Experiment

30 30 NEM-FET: true hybrid mechanical-solid-state switch with near-zero point subthreshold swing attractive for low-Ioff power management switches, capacitor-less memory (D-RAM, S-RAM and NVM with appropriate storage layers) and new analog/RF functionality (in the resonant-gate configuration). fabrication: compatibility of surface micromachining with CMOS processing. Voltage scaling below 1-2V: nanogap technology Size: ~as scalable as MOSFET (anchors needed) NEMFET does not use mechanical contacts in the path of current flow: long-term reliability comparable to that of capacitive RF MEMS switches (>10 9 cycles), being limited by oxide charging. Conclusion

31 31 MEMS/NEMS application roadmap NEM sensing

32 32 NEMS  Beyond CMOS = low power nano-switch  More than Moore = new functionality Key role of NEMS for power savings and new functionality: future hybrid NEMS-CMOS Future role of true hybrid NEM-FET devices: abrupt switch, memory, resonator, sensing Challenges for hybrid NEM-FET:  additional process control of nanoscale air-gap, thickness and uniformity of suspended structures, control and uniformity of mechanical properties  fabrication: top-down & bottom-up (Si, CNTs)  wafer-level packaging and reliability  thermal drift MEMS/NEMS application roadmap

33 33 Acknowledgments EPFL: FP7 IST projects MIMOSA, MINAMI and NANO-RF Stanford: DARPA, FCRP C2S2, NSF Roger T. Howe, David Elata, J Provine, Roozbeh Parsa, Kyeongran Yoo, Soogine Chong UC Berkeley: DARPA, FCRP C2S2 Hei Kam

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