Presentation on theme: "NEMS Devices OPPORTUNITIES AND CHALLENGES"— Presentation transcript:
1NEMS Devices OPPORTUNITIES AND CHALLENGES Adrian IonescuNanolab, EPFL Switzerland
2Goal of this talk…Prove that energy efficient nanolectronics is a must for the future…… and NEMS is a potential key enabling low power technology.
3Switch made for performance… Source: Heike Riel, IBM.
4… not for energy efficiency Power crisis in nanoelectronicsLeakage power dominates in advanced technology nodes.VT scaling saturated by 60mV/dec limit, voltage scaling slowed.1E-051E-041E-031E-021E-011E+001E+011E+021E+030.010.11Gate Length (μm)Passive Power DensityActive Power DensitySource: B. Meyerson (IBM)Semico Conf., January 2004Power Density (W/cm2)
5Today’s computing: energy/bit What matters:energy / computed bitscalingsystemabilitysystem level metrics prevail over device levelIntegrated approach for energy/bit at system level:SwitchMemoryInterconnectsArchitectureEmbedded Software
7Subthermal switches A fundamental issue? m less than 1 active gate devices:NEM relay or NEMFETnegative capacitancen less than (kT/q)ln10# injection in the channelTunnel FETsImpact Ionization MOS
8Nano-Electro-Mechanical (NEM) Devices NEM switchNEM memoryNEM resonators
9Electro-mechanical info processing as a multi-state logic, with the logic states dictated by a spatial configuration of movable objectsas vibrational modes of mechanical elements, based upon waves.as a sensed or transduced signal operation.
10NEMS simulation and modeling Source: G. Li et al, Urbana-Champaign.
11NEM relay as subthermal switch Advantages:- zero Ioff (zero static power).- abrupt transition between off and on states.(Unwanted?) feature of NEM switch:- hysteresis due to different values of pull-in, Vpi (off-on transition) and pull-out, Vpo (off-on transition) voltages.Pull-in voltage:
12MEMS process integration For low cost & high performance, post-CMOS integration is desirable.Thermal process budget is constrained for MEMS fabrication: surface micromachining is low TSi Substratefoundry CMOSMEMSSource: T.J. King.
14MEM logic relay Nice but large (10’s micrometer) size! Scalable? Source: V. Pott, T.J. King, UC Berkeley.
15Metal NW relays Nice, small size! Ioff excellent But voltage large: > 10VScalable?W. W. Jang et al, Appl. Phys. Lett., 92(10), , 2008.
16Relay-based IC design CMOS to real logic mappping 100x less energy per half-adderRelay technologyF. Chen et al, ICCAD 2008.
17Comms: energy per useful bit Energy / useful bit =transmit energy + transmitted energy + receive energyRole of MEMS/NEMS inlow power communications?10 2m~1000 less than SoA= signal processing +front-end= signal processing +front-end +sleep (“scan”) modePHY, MAC, NETW
18First MEMS memoryB. Halg, "On a micro-electro-mechanical nonvolatile memory cell", IEEE Transactions on Electron Devices, Vol. 37, Iss. 10, 1990.thin micromachinedbridge elastically deformed:two stable mechanicalstates : “0” and “1”MOS process: Si02 layer bridge covered by a 2nm thin Crstate of the bridge changed using electrostatic forcesread out by sensing the capacitanceSize: ~hundreds mm2Actuation voltage: > 40V
19Bistable NEM NV memory cell Y. Tsuchiya, K. Takai, N. Momo, T. Nagami, H. Mizuta, S. Oda, "Nanoelectromechanical nonvolatile memory device incorporating nanocrystalline Si dots", Journal of Applied Physics, 100, 2006.
20NEMORY cell concept (1) Nano-Electro-Mechanical NV memory W.Y. Choi; H. Kam; D. Lee, J. Lai, T.-J. King Liu, "Compact Nano-Electro-Mechanical Non-Volatile Memory (NEMory) for 3D Integration", Technical Digest of IEEE International Electron Devices Meeting, IEDM 2007.Nano-Electro-Mechanical NV memoryRWL as a top electrodeBL as a movable mechanical beam: information stored as BL positionONO stack for charge storageWWL as a lower electrode
21NEMORY cell conceptNEMory cell operation is based on the hysteretic behavior of a mechanical gap-closing actuator.Charge in the ONO layer is used to shift the hysteresis curves by Voffset, to achieve bistability at 0 V (VBL-WWL VBL - VWWL), thus enabling non-volatile storage.
22FinFACT –switch & memory J.W. Han, Jae-Hyuk Ahn, Min-Wu Kim, Jun-Bo Yoon, and Yang-Kyu Choi, "Monolithic Integration of NEMS-CMOS with a Fin Flip-flop Actuated Channel Transistor (FinFACT)", IEDM 2009.Principle: laterally movable (suspended) silicon FIN, bistable & sensed by transistor current flow.
23FinFACT (2)Depending on design (width) can be used both as NV (ROM) or SRAM.Trade-off between the endurance and retention.
24CNT-based memory cellJ.E. Jang et al, "Nanoscale memory cell based on a nanoelectromechanical switched capacitor", Nature Nanotechnology, Vol. 3, Jan. 2008, ppNEM switched capacitor structure based on vertically aligned MW CNTs- Capacit. of CNT NEM DRAM cell (diameter=60 nm; length=1.6 mm; SiNx,=40 nm): value of 0.59 fF with available potential of 2.4 mV for bit line sensing in a conventional DRAM design.15 fF and 60–80 mV (Gbit DRAM) possible by the integration of high-k (not shown)voltages > 14V
25NEMS memory figures of merit comparable cell areascalable/comparable operation voltageslowest program/erase energy: sub J/bit.
26NEM resonators Passive MEMS resonator Resonant body transistor Probably the most promising family of RF M/NEMS.Embedding full equivalent circuit functions (RLC) with very high-Q and voltage tuning (possible replacement of quartz).Applications: oscillators, mixing, filtering, sensing.Passive MEMS resonatorResonant body transistorAdrian Ionescu, GRC 201226
27Their scaling… Frequency, mass, Q mass & force detection Fully-depleted RB-FET:0.5 µm x 0.25 µm x 10 µmNanowire RB-FET:40 nm x 40 nm x 2 umNW-FET bodyFrequency, mass, Qmass & force detectionnm SOI-CMOS technologyintegration density, complexity400 nm
28Low power characteristics Tunable operation point:Trade-off: gain versus power.Experiment: resonance from strong to weak inversion.nW static power consumption in weak-inversion (PDC < PAC ).S. T. Bartsch, A.M. Ionescu, IEDM 2010.
29Vibrating body transistors Double-gate (in-plane) VB-FET resonator: transistor detection improves output signal by more than +30dB.TransistorCapacitiveD. Grogg et al, IEDM 2008.
30Full circuit functions… Transistor-based homodyne / heterodyne mixing.Mixing coupled to mechanical motion.Signal-to-background improvement.Applications: VHF mixer-filter, closed-loop configurations.Mixer output [a.u.]Frequency [MHz]Gate Votlage[V]Imix ~ gmCc-Beam: x 0.2 x 3 µm3f0=78 MHz, Q=1100S.T.Bartsch et al, ACS Nano 2011.
31Ultra-scaled single-NEM radio Highly sensitive integrated sensor arrays (~ attogram)Ultra miniaturized single-device radios (RF front ends)
32Vibrating body CNT FET Device concept: SW CNT instead of Si fres ~100MHz-1GHzstrong piezores. Effect 2xfDG, 100nm airgapBy resist-assisted DEP(>107 CNTs/cm2)A.M. Ionescu, IEDM 2011Adrian IonescuAdrian Ionescu, GRC 2012323232
33Nano-scale active mass balance Source: Ji Cao, EPFL.
34Summary (1) Energy efficient devices: a must for the future! Challenges:Relaysscaling of:gaps & sizeoperation voltagereliability of contacts & packagingdedicated IC designResonatorsanalog/RF & sensingNEMS
35Summary (2)NEM memory:exploit the. electromechanical hysteresis of movable structures by a gap closing Storage layer: specific purpose for shifting the hysteresis (NEMory, Oda’s memory, SG-FET)!excellent co-integration with silicon CMOS. Low temperature processing, BEOL (3D-) integration possible, low cost.Low voltage operation possible, limits ~1VProgram/erase & read times: <10nsenergy efficiency: less than J/bit in NEMory & SBM.Trade-off between endurance & retention in FIN-FACT.Robust in high temperature and radiation environments.CNT-based memory: immaturePromising for embedded memory applications