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Adrian Ionescu Nanolab, EPFL Switzerland 1. Prove that energy efficient nanolectronics is a must for the future… … and NEMS is a potential key enabling.

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Presentation on theme: "Adrian Ionescu Nanolab, EPFL Switzerland 1. Prove that energy efficient nanolectronics is a must for the future… … and NEMS is a potential key enabling."— Presentation transcript:

1 Adrian Ionescu Nanolab, EPFL Switzerland 1

2 Prove that energy efficient nanolectronics is a must for the future… … and NEMS is a potential key enabling low power technology. 2

3 Source: Heike Riel, IBM. 3

4 Power crisis in nanoelectronics Leakage power dominates in advanced technology nodes. V T scaling saturated by 60mV/dec limit, voltage scaling slowed. Power Density (W/cm 2 ) 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01 1E+02 1E Gate Length (μm) Passive Power Density Active Power Density Source: B. Meyerson (IBM) Semico Conf., January

5 What matters: energy / computed bit scaling systemability system level metrics prevail over device level Integrated approach for energy/bit at system level: Switch Memory Interconnects Architecture Embedded Software 5

6 V D =V dd VGVG 6

7 A fundamental issue? 7 n less than (kT/q)ln10 # injection in the channel Tunnel FETs Impact Ionization MOS m less than 1 active gate devices: NEM relay or NEMFET negative capacitance

8 Nano-Electro-Mechanical (NEM) Devices NEM switch NEM memory NEM resonators 8

9 9 as a multi-state logic, with the logic states dictated by a spatial configuration of movable objects as vibrational modes of mechanical elements, based upon waves. as a sensed or transduced signal operation.

10 10 Source: G. Li et al, Urbana-Champaign.

11 11 Advantages: - zero Ioff (zero static power). - abrupt transition between off and on states. (Unwanted?) feature of NEM switch: - hysteresis due to different values of pull-in, V pi (off-on transition) and pull-out, V po (off-on transition) voltages. Pull-in voltage:

12 12 For low cost & high performance, post-CMOS integration is desirable. Thermal process budget is constrained for MEMS fabrication: surface micromachining is low T Si Substrate foundry CMOS MEMS Source: T.J. King.

13 13 3-terminal relay: Stanford 4-terminal relay: UC Berkeley 2-terminal relay: EPFL

14 14 Source: V. Pott, T.J. King, UC Berkeley. Nice but large (10s micrometer) size! Scalable?

15 15 W. W. Jang et al, Appl. Phys. Lett., 92(10), , Nice, small size! Ioff excellent But voltage large: > 10V Scalable?

16 16 CMOS to real logic mappping Relay technology F. Chen et al, ICCAD x less energy per half-adder

17 17 Energy / useful bit = transmit energy + transmitted energy + receive energy = signal processing + front-end = signal processing + front-end + sleep (scan) mode 10 2m ~1000 less than SoA PHY, MAC, NETW Role of MEMS/NEMS in low power communications? Role of MEMS/NEMS in low power communications?

18 18 B. Halg, "On a micro-electro-mechanical nonvolatile memory cell", IEEE Transactions on Electron Devices, Vol. 37, Iss. 10, thin micromachined bridge elastically deformed: two stable mechanical states : 0 and 1 MOS process: Si0 2 layer bridge covered by a 2nm thin Cr state of the bridge changed using electrostatic forces read out by sensing the capacitance Size: ~hundreds m 2 Actuation voltage: > 40V

19 19 Y. Tsuchiya, K. Takai, N. Momo, T. Nagami, H. Mizuta, S. Oda, "Nanoelectromechanical nonvolatile memory device incorporating nanocrystalline Si dots", Journal of Applied Physics, 100, 2006.

20 20 Nano- E lectro- M echanical NV memory –RWL as a top electrode –BL as a movable mechanical beam: information stored as BL position –ONO stack for charge storage –WWL as a lower electrode W.Y. Choi; H. Kam; D. Lee, J. Lai, T.-J. King Liu, "Compact Nano-Electro- Mechanical Non-Volatile Memory (NEMory) for 3D Integration", Technical Digest of IEEE International Electron Devices Meeting, IEDM 2007.

21 21 NEMory cell operation is based on the hysteretic behavior of a mechanical gap-closing actuator. Charge in the ONO layer is used to shift the hysteresis curves by V offset, to achieve bistability at 0 V (V BL-WWL V BL - V WWL ), thus enabling non-volatile storage.

22 22 J.W. Han, Jae-Hyuk Ahn, Min-Wu Kim, Jun-Bo Yoon, and Yang-Kyu Choi, "Monolithic Integration of NEMS-CMOS with a Fin Flip-flop Actuated Channel Transistor (FinFACT)", IEDM Principle: laterally movable (suspended) silicon FIN, bistable & sensed by transistor current flow.

23 23 - Depending on design (width) can be used both as NV (ROM) or SRAM. - Trade-off between the endurance and retention.

24 24 NEM switched capacitor structure based on vertically aligned MW CNTs - Capacit. of CNT NEM DRAM cell (diameter=60 nm; length=1.6 m; SiNx,=40 nm): value of 0.59 fF with available potential of 2.4 mV for bit line sensing in a conventional DRAM design. -15 fF and 60–80 mV (Gbit DRAM) possible by the integration of high-k (not shown) - voltages > 14V J.E. Jang et al, "Nanoscale memory cell based on a nanoelectromechanical switched capacitor", Nature Nanotechnology, Vol. 3, Jan. 2008, pp

25 25 comparable cell area scalable/comparable operation voltages lowest program/erase energy: sub J/bit.

26 26 Adrian Ionescu, GRC Probably the most promising family of RF M/NEMS. Embedding full equivalent circuit functions (RLC) with very high-Q and voltage tuning (possible replacement of quartz). Applications: oscillators, mixing, filtering, sensing. Passive MEMS resonator Resonant body transistor

27 27 Frequency, mass, Q mass & force detection nm SOI-CMOS technology integration density, complexity Nanowire RB-FET: 40 nm x 40 nm x 2 um Fully-depleted RB-FET: 0.5 µm x 0.25 µm x 10 µm 400 nm NW-FET body

28 28 Tunable operation point: Trade-off: gain versus power. Experiment: resonance from strong to weak inversion. nW static power consumption in weak-inversion (P DC < P AC ). S. T. Bartsch, A.M. Ionescu, IEDM 2010.

29 29 Double-gate (in-plane) VB-FET resonator: transistor detection improves output signal by more than +30dB. D. Grogg et al, IEDM Capacitive Transistor

30 30 Transistor-based homodyne / heterodyne mixing. Mixing coupled to mechanical motion. Signal-to-background improvement. Applications: VHF mixer-filter, closed-loop configurations. I mix ~ g m S.T.Bartsch et al, ACS Nano Cc-Beam: 0.15 x 0.2 x 3 µm 3 f 0 =78 MHz, Q=1100

31 31 Highly sensitive integrated sensor arrays (~ attogram) Ultra miniaturized single-device radios (RF front ends)

32 32 Adrian Ionescu, GRC Adrian Ionescu32 A.M. Ionescu, IEDM 2011 Device concept: SW CNT instead of Si fres ~100MHz-1GHz strong piezores. Effect 2xf DG, 100nm airgap By resist-assisted DEP (>10 7 CNTs/cm 2 )

33 33 Source: Ji Cao, EPFL.

34 Energy efficient devices: a must for the future! Challenges: 34 NEMS Relays scaling of: gaps & size operation voltage reliability of contacts & packaging dedicated IC design Resonators analog/RF & sensing

35 NEM memory: exploit the. electromechanical hysteresis of movable structures by a gap closing Storage layer: specific purpose for shifting the hysteresis (NEMory, Odas memory, SG-FET)! excellent co-integration with silicon CMOS. Low temperature processing, BEOL (3D-) integration possible, low cost. Low voltage operation possible, limits ~1V Program/erase & read times: <10ns energy efficiency: less than J/bit in NEMory & SBM. Trade-off between endurance & retention in FIN-FACT. Robust in high temperature and radiation environments. CNT-based memory: immature Promising for embedded memory applications 35

36 36


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