Recovery Technique 1: Global Clock Gating If any stage detects a timing problem Stall the entire pipeline for one clock cycle. Use this additional clock cycle to recompute using the correct shadow-latch values
Recovery Technique 2: Counterflow Pipelining When a mismatch (between regular and shadow latch contents) is detected: Assert a bubble signal, to specify that the erring pipeline slot is now to be considered a bubble. In the subsequent cycle, inject the shadow latch value into the next stage, allowing the errant operation to continue with the correct values Trigger a flush train, traveling backwards from the errant stage, flushing operations at each stage it visits
Process Variation Impact on Memory Systems The process variations are random in nature and are expected to become significant in the smaller geometry transistors commonly used in memories. Process variations in caches affect the performance of circuits like Sense amplifiers that require identical device characteristics SRAM cells that require near-minimum-sized cell stability for large arrays in embedded, low-power applications The delay of the address decoders suffer from the process variations that can result in shorter time left for accessing the SRAM cells Question is whether there is a significant delay variation overall that will drive a change in memory architecture design.