1. Presenter: Dilip Vasudevan Supervisor: Dr.Aristides Efthymiou University of Edinburgh 1 September 2008 20 th UK Async Forum Manchester Partial Scan Test Generation for Asynchronous Circuits Based on Breaking Global Loops 1

2. Introduction Test Methodology Working Example Results Conclusion Synopsis 2

3. Introduction Main challenges faced by applying ATPG technique to the asynchronous circuits are Asynchronous circuits have loops which makes them cyclic circuit Asynchronous circuits consist of memory element(C-element) other than latches. The operation of C-element cannot be controlled during their normal operation compared to normal latch controlled by clock. 3

4. Contribution Effective handling of cyclic asynchronous circuits to accommodate them for the usual synchronous test generation flow Partial scan element selection based on Breaking global loops Global Loops broken by finding Strongly Connected Components Automatic Test Pattern Generation for the partial scan design generated The contribution of the project AGLOB is A Graph is Strongly Connected if there is a path from each vertex in the graph to every other vertex. 4

5. AGLOB 5

6. AGLOB – A Partial Scan Test g eneration for Asynchronous Circuits Based on G lobal LO op B reaking Partial scan selection -Finding Strongly Connected Components Global loops are broken by partial scan selection Local loops are broken by applying cyclic to acyclic conversion Fault simulation and test generation –Synopsys Tetramax 6

7. Cyclic Circuits with loops 7

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9. AGLOB Test Methodology Scan Selection Acyclic Converter Acyclic Netlist Tetramax Patterns DFT Netlist Fault Simulation Fault Coverage DUT Netlist Processing Local Loops Global Loops Broken 9

10. L(1)12 L(2)23 L(3)346 L(4)3467 First Pass Second Pass Scan Elements = {3} Scan Elements = {1,3} L(1)12 10

11. Test generation C-element – (LOCAL LOOP) ‏ 11

12. Global loop in the ramreadsbuf Gates Constituting the loop in ramreadsbuf 12

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14. 88.23 100 76.19 76.67 77.78 89.19 91.23 92.77 76.78 96.34 76.78 96.25 90.36 - 100 97 85.7 100 97.1 96.9100 100 94.9 - 40.0 87.9 21.4 100 97.1 96.9 100 59.3 26 22 48 40 25 56 54 60 82 90 62 110 94 C-element Half Hazard dff rcv-setup chu150 chu133 mp-forw-pack nak-pa ram-read-buf rpdft sbuf-ram-write sbuf-send-ctrl Proposed[SS]E Fault coverageNo of faults Benchmark Results – AGLOB E – Eichelberger's SS - Spin-Sim TABLE I Fault Coverage Comparison of proposed method with Eichelberger's method and Spin SIM 14

15. Results - AGLOB TABLE II Result – Fault Coverage Comparison of proposed methods with Latch Free, latch based designs 3 local90.3694.1616.20Sbu-send-ctrl 2 local96.2595.0022.79sbuf-ram-write 1g,2local96.3493.2940.71ram-read-buf 1g,1local92.7795.1869.57mp-forward- packet 2 local89.1990.1523.33chu150 1 local91.2385.7145.56chu133 LoopsProposed FC (%)‏ Full-scan FC (%) Latch free FC (% ) Benchmark 15

16. Fig 9. Scan latch Overhead Reduction in percentage Results - AGLOB 16

17. CONCLUSIONS A Partial Scan based ATPG method for was introduced Fault coverage - 76- 100% Scan Area Overhead reduction - 0 – 66% (compared to full scan) ‏ Future work - Transistor Level Test Generation with new Fault Model 17

18. Thank You! 18