1. Partial Scan Design with Guaranteed Combinational ATPG Vishwani D. Agrawal Agere Systems, Circuits and Systems Research Lab Murray Hill, NJ 07974, USA va@agere.com Yong C. Kim and Kewal K. Saluja University of Wisconsin, Dept. of ECE Madison, WI 53706, USA kimy@ece.wisc.edukimy@ece.wisc.edu and saluja@engr.wisc.edu saluja@engr.wisc.edu kimy@ece.wisc.edusaluja@engr.wisc.edu

2. Partial scan with comb. ATPG 2 Aug. 21, 2001 Overview 1. Problem statement 2. Background and previous work 3. Combinational ATPG for general acyclic circuits Balanced model generation Balanced model generation Test generation – multiple-fault model Test generation – multiple-fault model Results Results 4. Special classes of acyclic circuits Internally balanced structure Internally balanced structure Balanced structure Balanced structure Strongly balanced structure Strongly balanced structure Results Results 5. Conclusion

3. Partial scan with comb. ATPG 3 Aug. 21, 2001 Problem Statement Partial scan design has less DFT overhead, but is less desirable than full-scan because it requires sequential ATPG Partial scan design has less DFT overhead, but is less desirable than full-scan because it requires sequential ATPG Problem: To devise a combinational ATPG method for general acyclic circuits; cyclic structures can be made acyclic by partial scan Problem: To devise a combinational ATPG method for general acyclic circuits; cyclic structures can be made acyclic by partial scan FF1 FF2 A cyclic circuitAcyclic partial scan circuit

4. Partial scan with comb. ATPG 4 Aug. 21, 2001 Background and Previous Work Models for Acyclic Sequential Circuits Iterative array model (Kunzmann and Wunderlich, JETTA, 1990): Logic duplicated as many times as sequential depth for combinational ATPG Iterative array model (Kunzmann and Wunderlich, JETTA, 1990): Logic duplicated as many times as sequential depth for combinational ATPG Duplicated logic model (Miczo, 1986): Selective logic duplication still results in large combinational ATPG circuit Duplicated logic model (Miczo, 1986): Selective logic duplication still results in large combinational ATPG circuit Pseudo-combinational model (Min and Rogers, JETTA, 1992): Shorting of flip-flops makes some faults combinationally untestable Pseudo-combinational model (Min and Rogers, JETTA, 1992): Shorting of flip-flops makes some faults combinationally untestable Balanced structure (Gupta, et al., IEEETC, 1990): A sequential circuit structure with provable fault detection by combinational ATPG Balanced structure (Gupta, et al., IEEETC, 1990): A sequential circuit structure with provable fault detection by combinational ATPG

5. Partial scan with comb. ATPG 5 Aug. 21, 2001 Relevant Results Theorem (Bushnell and Agrawal, 2000): A test for a testable non-flip-flop fault in a cycle-free (acyclic) circuit can always be found with at most d seq +1 time-frames. Theorem (Bushnell and Agrawal, 2000): A test for a testable non-flip-flop fault in a cycle-free (acyclic) circuit can always be found with at most d seq +1 time-frames. Balanced circuit (Gupta, et al., IEEETC, 1990): An acyclic circuit is called balanced if all paths between any pair of nodes have the same sequential depth. A test for any testable fault in a balanced circuit can be found by combinational ATPG. Balanced circuit (Gupta, et al., IEEETC, 1990): An acyclic circuit is called balanced if all paths between any pair of nodes have the same sequential depth. A test for any testable fault in a balanced circuit can be found by combinational ATPG.

6. Partial scan with comb. ATPG 6 Aug. 21, 2001 Present Contribution: Comb. ATPG for General (Unbalanced) Acyclic Circuits Generate a balanced model, map faults Done No Generate a test vector for a target fault using combinational ATPG Obtain a test sequence from comb. vector Simulate circuit to drop detected faults More faults to be detected? Yes

7. Partial scan with comb. ATPG 7 Aug. 21, 2001 An Example FF Unbalanced nodes s-a-0 FF replaced by buffer s-a-0 a b a0a0 b0b0 a -1 b -1 Balanced model 0 X 1 1 Combinational vector 0 1/0 1 Test sequence: 11, 0X d seq = 1

8. Partial scan with comb. ATPG 8 Aug. 21, 2001 A Single Fault Model for a Multiple Fault (New) s-a-1 A B C b c a An equivalent single stuck-at fault : output of AND gate stuck-at 1 Multiple stuck-at fault : lines a and b stuck-at 1 and line c stuck-at 0. A B C b c a s-a-1 s-a-0

9. Partial scan with comb. ATPG 9 Aug. 21, 2001 Proof of Correctness for the New Model Circuit equivalence: Fault-free output functions Circuit equivalence: Fault-free output functions A = a + a ·b ·!c = a B = b + a ·b ·!c = b B = b + a ·b ·!c = b C = c ·!(a ·b ·!c) = c · (!a + !b + c) =c ·(!a + !b) + c = c C = c ·!(a ·b ·!c) = c · (!a + !b + c) =c ·(!a + !b) + c = c s-a-1 A B C b c a A B C b c a s-a-0 Fault equivalence: Faulty output functions Fault equivalence: Faulty output functions A mf = 1 B mf = 1 B mf = 1 C mf = 0 C mf = 0 Fault equivalence: Faulty output functions Fault equivalence: Faulty output functions A sf = a + 1 = 1 B sf = b + 1 = 1 B sf = b + 1 = 1 C sf = c · 0 = 0 C sf = c · 0 = 0 s-a-1 A B C b c a

10. Partial scan with comb. ATPG 10 Aug. 21, 2001 6 2 5 4 3 X7 FF2 1 D Q A B C FF1 D Q FF3 FF4 Y D Q FF2 1 0 6 2 5 4 3 X7 1 D Q FF1 D Q FF3 FF4 Y D Q FF2 1 0 1 0 1 A TF=1 B A TF=0 B B TF=2 C Acyclic Circuit Combinational ATPG Example 6 2 5 4 3 X7 FF2 1 D Q FF1 D Q FF3 FF4 Y D Q FF2 1 0 1 0 1 A TF=1 B A TF=0 B C TF=1 B TF=2 C 6 2 5 4 3 X7 FF2 1 D Q A B C FF1 D Q FF3 FF4 Y Multiple fault mapping: A stuck-at fault of 1 is mapped onto a multiple fault 6 2 5 4 3 X7 FF2 1 FF1 FF3 FF4 Y FF2 1 0 1 0 1 A B A B C B C

11. Partial scan with comb. ATPG 11 Aug. 21, 2001 ISCAS ’89 Benchmark Circuit Result: S5378 Circuit statistics Circuit statistics Number of gates: 2,781 Number of gates: 2,781 Number of FFs: 179 Number of FFs: 179 Number of faults: 4,603 Number of faults: 4,603 * Sun Ultra Sparc work station

12. Partial scan with comb. ATPG 12 Aug. 21, 2001 ISCAS’89 Circuits (Acyclic with Partial Scan) FC: cov. (%), FC: efficiency (%), VL: vec. Length, TGT: CPU s Sun Ultra

13. Partial scan with comb. ATPG 13 Aug. 21, 2001 ISCAS’89 Circuits (Acyclic with Partial Scan) Circuit statistics

14. Partial scan with comb. ATPG 14 Aug. 21, 2001 Acyclic Subclasses of Acyclic Circuits Internally balanced (IB) circuit: A circuit that becomes balanced by splitting of PI fanouts (Fujiwara et al., IEEETC, 2000) Acyclic circuit: A sequential circuit without feedback Acyclic circuit: A sequential circuit without feedback Balanced (B) circuit: A circuit in which all paths between any pair of nodes (PIs, POs, gates or FFs) have the same sequential depth (Gupta et al, IEEETC, 1990) Balanced (B) circuit: A circuit in which all paths between any pair of nodes (PIs, POs, gates or FFs) have the same sequential depth (Gupta et al, IEEETC, 1990) Strongly Strongly balanced (SB) circuit: A balanced circuit which has same depth from any PIs to any reachable POs (Balakrishnan and Chakradhar, VLSI Design `96) Combinational circuit: A sequential circuit with full-scan Combinational circuit: A sequential circuit with full-scan Sequential IB SB B Combinational

15. Partial scan with comb. ATPG 15 Aug. 21, 2001 Number of Scan FFs for Various Subclasses IB: Internally balanced (Fujiwara, IEEETC, 2000) B: Balanced (Gupta, et al., IEEETC, 1990) SB: Strongly balanced (Balakrishnan and Chakradhar, VLSI Design ’96)

16. Partial scan with comb. ATPG 16 Aug. 21, 2001 Fault Coverage for Acyclic Subclasses ATPG: Gentest (Cheng and Chakraborty, Computer, 1989)

17. Partial scan with comb. ATPG 17 Aug. 21, 2001 ATPG CPU Seconds for Acyclic Subclasses (Sun Ultra Workstation) ATPG: Gentest (Cheng and Chakraborty, Computer, 1989)

18. Partial scan with comb. ATPG 18 Aug. 21, 2001 Comb. And Sequential Vector Lengths VL: Number of combinational ATPG vectors CC: Sequential test clock cycles for scan sequences Acyclic BalancedInternally bal.Strongly bal.Combinational

19. Partial scan with comb. ATPG 19 Aug. 21, 2001 Conclusion Using a balanced circuit model and combinational ATPG, we can generate tests for any acyclic sequential circuit with equal or higher fault coverage and efficiency than obtained by sequential ATPG. Using a balanced circuit model and combinational ATPG, we can generate tests for any acyclic sequential circuit with equal or higher fault coverage and efficiency than obtained by sequential ATPG. For acyclic circuits, the new ATPG procedure provides comparable fault coverage and efficiency with significantly lower DFT ( partial- scan) overhead as compared to internally balanced, balanced, strongly balanced and combinational subclasses. For acyclic circuits, the new ATPG procedure provides comparable fault coverage and efficiency with significantly lower DFT ( partial- scan) overhead as compared to internally balanced, balanced, strongly balanced and combinational subclasses.

20. Partial scan with comb. ATPG 20 Aug. 21, 2001 Thank you