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May 9, 20012 High-Speed Detection Handshake Considerations Jerome Tjia Philips Semiconductors Jerome Tjia Philips Semiconductors.

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Presentation on theme: "May 9, 20012 High-Speed Detection Handshake Considerations Jerome Tjia Philips Semiconductors Jerome Tjia Philips Semiconductors."— Presentation transcript:

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2 May 9, High-Speed Detection Handshake Considerations Jerome Tjia Philips Semiconductors Jerome Tjia Philips Semiconductors

3 May 9, Why This Topic? w Chirping process is the pre-requisite to high- speed operation (failure in chirping process defaults back to FS/LS mode) w A few “gotchas” in the implementation w If not properly designed, it will become a major interoperability issue w Chirping process is the pre-requisite to high- speed operation (failure in chirping process defaults back to FS/LS mode) w A few “gotchas” in the implementation w If not properly designed, it will become a major interoperability issue

4 May 9, Reset/Speed Detection Protocol w High-speed capable devices are reset by 10ms of continuous SE0 (same as USB 1.1) w During Reset, a high-speed capable device “chirps” to the hub w If a USB 2.0 hub detects this chirp, it completes the handshake by chirping back to the device within the Reset w If the handshake is completed during Reset, both hub and device come out of Reset in high-speed mode w High-speed capable devices are reset by 10ms of continuous SE0 (same as USB 1.1) w During Reset, a high-speed capable device “chirps” to the hub w If a USB 2.0 hub detects this chirp, it completes the handshake by chirping back to the device within the Reset w If the handshake is completed during Reset, both hub and device come out of Reset in high-speed mode

5 May 9, Reset Handshake Signaling w Device chirp is a Chirp K (detected with hub’s high-speed receiver) w Device chirps by driving current in D- line while leaving D+ pullup in place and leaving terminations inactive w Hub chirp is a series of alternating Chirp J’s and K’s w Hub chirps by driving current into D+ or D- line w Reference state machines included in Appendix C w Device chirp is a Chirp K (detected with hub’s high-speed receiver) w Device chirps by driving current in D- line while leaving D+ pullup in place and leaving terminations inactive w Hub chirp is a series of alternating Chirp J’s and K’s w Hub chirps by driving current into D+ or D- line w Reference state machines included in Appendix C

6 May 9, Timeline for Reset μSOF Device Chirp Hub Chirp D+ D– ms μs< 500 μs> 1.0 ms < 7.0 ms < 100 μs μs > 10 ms End of Device Chirp Start of Device Chirp Start of Reset Device reverts to FS Device reverts to HS Device detects Hub Chirp Start of Reset End of Reset End of Hub Chirp Start of Hub Chirp μSOF Hub Device SE0SE0SE0 HS idle

7 May 9, A Closer Look at SE0 Level During Reset w During reset, SE0 level are not exactly at ground w 1.5 k ohm pull-up resistor on D+ is not disconnected yet w Results in a little offset voltage w During reset, SE0 level are not exactly at ground w 1.5 k ohm pull-up resistor on D+ is not disconnected yet w Results in a little offset voltage

8 May 9, USB 2.0 Transceiver Functionality

9 May 9, DC Condition During Reset

10 May 9, DC Voltage Levels During Reset w DC Voltage at D+/D- lines: – V D- = 0V – V D+ = V TERM * (Z HSDRV // R PD ) / ((Z HSDRV // R PD ) + R PU ) w V D+ (min, typ, max) voltage = (79, 96, 120) mV – V TERM = 3.3 +/- 0.3V – Z HSDRV = 45 ohm +/- 10% – R PU = 1k5 +/- 5% – R PD = 15k +/- 5% w This offset voltage is termed “Tiny-J” w DC Voltage at D+/D- lines: – V D- = 0V – V D+ = V TERM * (Z HSDRV // R PD ) / ((Z HSDRV // R PD ) + R PU ) w V D+ (min, typ, max) voltage = (79, 96, 120) mV – V TERM = 3.3 +/- 0.3V – Z HSDRV = 45 ohm +/- 10% – R PU = 1k5 +/- 5% – R PD = 15k +/- 5% w This offset voltage is termed “Tiny-J”

11 May 9, Will Tiny-j Become Valid J? w Two conditions to become valid-J: – Differential receiver able to indicate J data – Squelch threshold must be crossed to indicate valid data w Differential receiver is normally very sensitive – Though spec is 150 mV (differential) – A tiny-J of 96 mV typical voltage level will most likely be detected as a ‘J’ w Squelch threshold may potentially be crossed too w Very likely that tiny-J be interpreted as a valid J w Two conditions to become valid-J: – Differential receiver able to indicate J data – Squelch threshold must be crossed to indicate valid data w Differential receiver is normally very sensitive – Though spec is 150 mV (differential) – A tiny-J of 96 mV typical voltage level will most likely be detected as a ‘J’ w Squelch threshold may potentially be crossed too w Very likely that tiny-J be interpreted as a valid J

12 May 9, Overlapping Squelch Threshold and Tiny-J levels 79 mV 120 mV 100 mV 150 mV Squelch threshold Tiny-J level

13 May 9, High-Speed Detection Handshake

14 May 9, Warning #1: Hub/host Should Ignore Tiny-J w During reset, hub/host is looking for a chirp-K w Potentially, it can receive a valid chirp-J w Hub/host should ignore this chirp-J – It should not reject or decide that the attached device is not high-speed capable at this time w It should continue to listen for a chirp-K for 7 ms or until the end of reset period w During reset, hub/host is looking for a chirp-K w Potentially, it can receive a valid chirp-J w Hub/host should ignore this chirp-J – It should not reject or decide that the attached device is not high-speed capable at this time w It should continue to listen for a chirp-K for 7 ms or until the end of reset period

15 May 9, Warning #2: End of Chirp-K Timing w End of chirp-K is another tiny-J level! w Cannot rely solely on squelch detector deassertion as the marker for end of chirp-K w Use non zero data pattern to indicate end of chirp-K w End of chirp-K -> alternating chirps K,J w End of chirp-K is another tiny-J level! w Cannot rely solely on squelch detector deassertion as the marker for end of chirp-K w Use non zero data pattern to indicate end of chirp-K w End of chirp-K -> alternating chirps K,J

16 May 9, Warning #3: Transceiver Design Guideline w Although tiny-J can be handled by upper digital logic layer of the host/hub, it’s double assurance to tackle it in the transceiver w To ensure that tiny-J is not interpreted as a valid J – ensure squelch threshold higher than tiny-J, by: – Increasing (doubling) squelch threshold during chirping period (will this violate spec?) OR – Designing squelch threshold voltage to be mV (tough?, no noise margin) w Although tiny-J can be handled by upper digital logic layer of the host/hub, it’s double assurance to tackle it in the transceiver w To ensure that tiny-J is not interpreted as a valid J – ensure squelch threshold higher than tiny-J, by: – Increasing (doubling) squelch threshold during chirping period (will this violate spec?) OR – Designing squelch threshold voltage to be mV (tough?, no noise margin)

17 May 9, Overlapping Squelch Threshold and Tiny-J levels 79 mV 120 mV 100 mV 150 mV Squelch threshold Tiny-J level

18 May 9, Other/minor Warnings - Device w Device starts driving chirp-K upon detection of reset signaling w Device Reset can happen from different states – Reset from (FS) suspended state – Reset from FS non-suspended state – Reset from HS non-suspended state w Reset from HS non-suspended state – initially indistinguishable from suspend – wait for 3 ms, switch to FS, wait TWTRSTHS (~ 500 us) debounce and settling time and then detects SE0 w Device starts driving chirp-K upon detection of reset signaling w Device Reset can happen from different states – Reset from (FS) suspended state – Reset from FS non-suspended state – Reset from HS non-suspended state w Reset from HS non-suspended state – initially indistinguishable from suspend – wait for 3 ms, switch to FS, wait TWTRSTHS (~ 500 us) debounce and settling time and then detects SE0

19 May 9, Timeline for Reset μSOF Device Chirp Hub Chirp D+ D– ms μs< 500 μs> 1.0 ms < 7.0 ms < 100 μs μs > 10 ms End of Device Chirp Start of Device Chirp Start of Reset Device reverts to FS Device reverts to HS Device detects Hub Chirp Start of Reset End of Reset End of Hub Chirp Start of Hub Chirp μSOF Hub Device SE0SE0SE0 HS idle

20 May 9, Summary w Specification is OK as is w Tiny-J needs to be taken care of properly w Watch out for warnings/gotchas in transceiver, host/hub and device design w Will become a major interoperability issue if not properly designed w Specification is OK as is w Tiny-J needs to be taken care of properly w Watch out for warnings/gotchas in transceiver, host/hub and device design w Will become a major interoperability issue if not properly designed


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