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May 8, 20012 High Speed Electrical Testing Jim Choate Intel Corporation.

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Presentation on theme: "May 8, 20012 High Speed Electrical Testing Jim Choate Intel Corporation."— Presentation transcript:


2 May 8, 20012 High Speed Electrical Testing Jim Choate Intel Corporation

3 May 8, 20013 Agenda w Electrical Testing Goals w Test Modes w Electrical Testing Procedures w Problems to Avoid w Summary

4 May 8, 20014 Goals of the Electrical Compliance Program w High Quality USB Products w Stable, Repeatable, Well Documented Tests – Documented Equipment Setups – Documented Test Procedures – Documented Test Assertions and Descriptions w Leverage USB FS/LS Electrical Tests – FS and LS Electrical Testing (LS for downstream ports) – Inrush – Drop and Droop

5 May 8, 20015 New Testing Areas w Electricals – High Speed Signal Quality – Time Domain Reflectometry (TDR) – Receiver Sensitivity and Squelch – J and K Voltage Levels – ChIRP HS Electrical Test Spec On USB-IF Members Site – Disconnect thresholds – Packet Parameters – Suspend/Resume – High Speed Hub Parameters u Sync truncation u EOP dribble u etc w USB High Speed Electrical Testing Starts at a High Level

6 May 8, 20016 USB HS Electrical Test Modes w High-speed Capable Devices/Hubs Must Support Test Modes

7 May 8, 20017 General HS Electrical Test Procedure w Connect Device Under Test To Test Port on Fixture w Configure DUT With Test Mode SW w Isolate DUT from Host with High Speed Relay w Make Appropriate Electrical Measurements

8 May 8, 20018 USB HS Test Fixture HS Relay Test Port InitializationPort Diff Probe DataGenerator 90 Ohms PowerSelectionCktPowerSelectionCkt Vbus1Vbus2 Vcc Gnd New Test Fixture(s) w Signal Quality w TDR w Receiver Sensitivity w ChIRP w J and K Levels w Disconnect threshold w Packet parameters w Suspend & Resume w Test Modes

9 May 8, 20019 High Speed Device Signal Quality Test Fixture Test Port Init Port To Host Controller To Host Controller To Device Under Test To Device Under Test Isolation relay power Test Switch Diff Probe Test Point New Test Fixture(s)

10 May 8, 200110 90 90 HS Signal Quality Test Procedure w Put Device in Test Mode Test_Packet – Flip Test Fixture Relays To Route Output to 90 Ohm Termination – Capture Waveform on oscilloscope – Analyze data w Data analysis is performed by generating an eye pattern Test Mode SW Oscilloscope USB HS Test Fixture HS Relay Differential Probe Device Under Test Test

11 May 8, 200111 Eye Pattern Generation w Time vs. voltage test packet data is transferred from scope to PC through GPIB

12 May 8, 200112 Eye Pattern Generation w Signal analysis scripts determine data rate from zero volt crossovers – Crossovers indicated at zero crossings below w Mean bit time calculated w Reference frame created from mean

13 May 8, 200113 Eye Pattern Generation w Reference frame position is optimized by minimizing least squares error between reference frame and actual crossovers Reference points between runs ignored Optimized reference point Actual crossover

14 May 8, 200114 1 bit time Eye Pattern Generation w Data is parsed into bit time internals using optimized reference frame w Eye pattern created from bit time intervals

15 May 8, 200115 Passing Eye Pattern w Example of passing High Speed Eye - Host Controller at TP2

16 May 8, 200116 Failing Eye Patterns w Min/Max voltage level failure w Caused by out of spec HS termination w Jitter failure w Caused by noise from power supply

17 May 8, 200117 HS Device Receiver Sensitivity and Squelch Test Procedure w DUT is Placed In Test_SEO_NAK Test Mode using Test Mode SW w The test fixture replaces the host by switching the connection to the Data Generator w Data Generator Generates IN Packets w Device Must Respond for In Spec Packets w Device Must Not Respond to Out of Spec Data Generator Output Data Generator Test Mode SW USB 2.0 Test Fixture HS Relay Device under test test SMA

18 May 8, 200118 w Device response to nominal packets w Device response to minimum packets w Device must not respond to packets below squelch threshold HS Device Receiver Sensitivity and Squelch Test Results DG packet Device Response No Device Response Minimum Receiver sensitivity threshold

19 May 8, 200119 TDR Test Procedure w Device Under Test Placed In Test_SEO_NAK Mode w Relay Switches Idle Data Lines to TDR w TDR Broadcasts Test Signal w TDR Measures Signal Reflections To Determine Termination And PCB Impedance TDR Test Mode SW USB 2.0 Test Fixture HS Relay Device Under Test Test SMA

20 May 8, 200120 Open voltage step indicates connector reference location TDR Test Procedure w Determining connector reference location – TDR connected to test fixture – Test fixture disconnected from device under test – Voltage step occurs at connector end (open step)

21 May 8, 200121 ZHSTHRU 70 to 110 Ohms (red cursors) ZHSTERM 80 to 100 Ohms (yellow region) USB connector Excursion of ZHSTHRU passes using exception window TDR Test Procedure w Measuring TDR response

22 May 8, 200122 Violates ZHSTHRU for > 800ps TDR Test Procedure w TDR Test Fails – Cause: Using a ribbon cable between the PCB & USB connector

23 May 8, 200123 Other Test Modes w Test_J & Test_K – Port enters and remains in the high-speed J or K state – Allows testing of output voltage and impedance when each output is high or low w Test Force Enable – Allows testing disconnect

24 May 8, 200124 Conclusions w High Speed Electrical Testing is Comprehensive – Electrical Testing u HS Signal Quality u TDR u Receiver Sensitivity u Suspend/Resume – Repeater Testing u Sync truncation, EOP dribble, etc w Well Documented Tests – Test Procedures – Test Specifications

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