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May 17, 20002 Electrical Detail Marq Kole Royal Philips Electronics Jon Lueker Intel Corporation.

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Presentation on theme: "May 17, 20002 Electrical Detail Marq Kole Royal Philips Electronics Jon Lueker Intel Corporation."— Presentation transcript:

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2 May 17, Electrical Detail Marq Kole Royal Philips Electronics Jon Lueker Intel Corporation

3 May 17, Speed Detection, Reset, and Suspend / Resume in USB 2.0

4 May 17, Contents w High-speed Capability Detection w Reset w Suspend w Reset from suspend w Resume

5 May 17, High-Speed Capability Detection w High-speed capability detection is performed during the reset period w All high-speed capable devices initially connect at full-speed – The rest of the system may not be high-speed capable

6 May 17, Reset w USB 1.1 Reset protocol is extended with reset signaling for high-speed hubs and devices w Extensions are compatible with USB 1.1: – Any USB 1.1 host/hub is able to reset any USB 2.0 hub/device – Additional Speed Detection Mechanism does not confuse a USB 1.1 hub/device w Reset of a high-speed device takes the same 10 ms minimum duration as USB 1.1 devices

7 May 17, Reset Handshake w High-speed capable hubs and devices perform a handshake to detect each others high-speed capabilities; w A High-speed Capable Device will initiate the handshake (“Hello, I can do High-speed”); w A High-speed Capable Hub responds to the handshake (“Great, I can do High-speed, too”); w After the handshake, both will communicate in High-speed mode. w Reference implementation in Appendix C

8 May 17, Timeline for Reset μSOF Device Chirp Hub Chirp D+ D– ms μs< 500 μs> 1.0 ms < 7.0 ms < 100 μs μs > 10 ms End of Device Chirp Start of Device Chirp Start of Reset Device reverts to FS Device reverts to HS Device detects Hub Chirp Start of Reset End of Reset End of Hub Chirp Start of Hub Chirp μSOF Hub Device SE0SE0SE0 HS idle

9 May 17, SE0 & T1  T WTRSTHS Reset State Diagrams HS Default HS Address HS Configured Start timer T0 Remove HS term. Connect D+ pull-up Start timer T1 idle!idle!idle T0  T WTREV !Resetting!Resetting ResettingResetting Drive SE0 Start timer T0 Clear timer T1 Run timer T1 SetPortFeature(PORT_RESET) HS K & PORT_LOW_SPEED = 0 !HS K & T1 < T FILT & T0 < T DETUCH !HS K & T1  T FILT Drive Chirp K Start timer T2 T2  T UCH Stop Chirp K Clear counter C0 Start timer T3 DeviceDevice HubHub HS Default HS Address HS Configured Start timer T0 Remove HS term. Connect D+ pull-up Start timer T1 idleidle T0  T WTREV !Resetting!Resetting ResettingResetting Drive SE0 Start timer T0 Clear timer T1 Run timer T1 SetPortFeature(PORT_RESET) HS K & PORT_LOW_SPEED = 0 !HS K & T1  T FILT Drive Chirp K Start timer T2 T2  T UCH Stop Chirp K Clear counter C0 Start timer T3 HS Default HS Address HS Configured Run timer T1 Drive SE0 Start timer T0 Clear timer T1 Drive Chirp K Start timer T2

10 May 17, Drive Chirp K Start timer T2 Reset State Diagrams (cont.) HS Default Clear timer T4 Increase C0 Run timer T4 Clear timer T4 Run timer T4 T4  T FILT HS K !HS K & T4 < T FILT HS J !HS J & T4 < T FILT Enable HS term. Disconnect D+ pull-up C0 < 3 & T3 < T WTFS C0  3 Drive Chirp K Start timer T2 HS Default T0  T DRST !HS K & T1  T FILT Drive Chirp J Start timer T2 Drive SE0 T2  T DCHBIT & T0  T DRST - T DCHSE0 T2  T DCHBIT & T0 < T DRST - T DCHSE0 DeviceDevice HubHub Clear timer T4 Increase C0 Run timer T4 Clear timer T4 Run timer T4 T4  T FILT HS K HS J C0 < 3 & T3 < T WTFS Drive Chirp K Start timer T2 !HS K & T1  T FILT Drive Chirp J Start timer T2 T2  T DCHBIT & T0 < T DRST - T DCHSE0 Clear timer T4 Drive Chirp K Start timer T2 Drive Chirp J Start timer T2 T2  T DCHBIT & T0 < T DRST - T DCHSE0 T4  T FILT HS K HS J T2  T DCHBIT & T0 < T DRST - T DCHSE0 Increase C0 Run timer T4

11 May 17, Drive Chirp K Start timer T2 Clear timer T4 Reset State Diagrams (cont.) HS Default Increase C0 Run timer T4 Clear timer T4 Run timer T4 T4  T FILT HS K !HS K & T4 < T FILT HS J !HS J & T4 < T FILT Enable HS term. Disconnect D+ pull-up C0 < 3 & T3 < T WTFS C0  3 HS Default T0  T DRST !HS K & T1  T FILT Drive Chirp J Start timer T2 Drive SE0 T2  T DCHBIT & T0  T DRST - T DCHSE0 T2  T DCHBIT & T0 < T DRST - T DCHSE0 DeviceDevice HubHub HS Default Enable HS term. Disconnect D+ pull-up C0  3 Increase C0 Run timer T4 Clear timer T4 Run timer T4 T4  T FILT HS K HS J Drive Chirp J Start timer T2 T2  T DCHBIT & T0 < T DRST - T DCHSE0 Clear timer T4 Drive Chirp J Start timer T2 T2  T DCHBIT & T0 < T DRST - T DCHSE0 T4  T FILT HS K HS J T2  T DCHBIT & T0 < T DRST - T DCHSE0 Increase C0 Run timer T4

12 May 17, Drive Chirp K Start timer T2 Reset State Diagrams (cont.) HS Default Clear timer T4 Increase C0 Run timer T4 Clear timer T4 Run timer T4 T4  T FILT HS K !HS K & T4 < T FILT HS J !HS J & T4 < T FILT Enable HS term. Disconnect D+ pull-up C0 < 3 & T3 < T WTFS C0  3 HS Default T0  T DRST !HS K & T1  T FILT Drive Chirp J Start timer T2 Drive SE0 T2  T DCHBIT & T0  T DRST - T DCHSE0 T2  T DCHBIT & T0 < T DRST - T DCHSE0 DeviceDevice HubHub HS Default Drive SE0 T0  T DRST T2  T DCHBIT & T0  T DRST - T DCHSE0 Drive Chirp J Start timer T2 T2  T DCHBIT & T0 < T DRST - T DCHSE0 Drive Chirp J Start timer T2 T2  T DCHBIT & T0 < T DRST - T DCHSE0 HS Default

13 May 17, Speed Detection Signaling w Signaling during reset with the high-speed driver in a full-speed configuration w Chirp K/J to distinguish from normal HS/FS/LS signaling Chirp K Generated by HS Device D+ D- RSRS RSRS RSRS RSRS R PU I HS Device Hub

14 May 17, Speed Detection Signaling (cont.) w Chirp K: -0.9 – -0.5 V (differential) w Chirp J: 0.7 – 1.1 V (differential) Chirp K Generated by HS Hub D+D+ D-D- RSRSRSRS RSRSRSRS RSRSRSRS RSRSRSRS R PU I HS DeviceDevice HubHub

15 May 17, Implementation w Implementation of Reset Protocol: – Requires very few additional gates – Has very loose timing requirements (system clock not required!) – Does not require logic at serial clock rate (possible at parallel interface) w Result: Reset Protocol can be implemented in many different ways – Hardware, software, firmware, digital, analog, etc.

16 May 17, Suspend w High-speed idle is identical to SE0 – Suspend initially indistinguishable from reset w Only after reverting to full-speed a HS device can make the distinction between idle and SE0

17 May 17, Timeline for Suspend FS idle SE μs ms Device reverts to HS Start of Inactivity μSOF HS Hub HS Device D– D+ Device goes into suspend Start of Suspend Signaling

18 May 17, Reset from Suspend w Reset of a suspended device should wake up that device from suspend w Low-power consumption makes fast start-up from suspend a challenge – No HS clock, no current reference w Reset protocol designed to do all handshake signaling without a stable clock – Very relaxed timing and voltage specs w Do not use the single-ended FS receivers for this!

19 May 17, Timeline for Reset from Suspend FS idle Device Chirp Hub Chirp D– > 2.5 μs< 500 μs> 1.0 ms < 7.0 ms < 100 μs μs > 10 ms End of Device ChirpStart of Device Chirp Start of Reset Device reverts to HS Device detects Hub Chirp Start of Reset End of Reset End of Hub Chirp Start of Hub Chirp μSOF HS Hub D+ HS Device SE0SE0 HS idle SE0

20 May 17, Resume w High-speed devices that were suspended from high-speed operation resume to high-speed w No need for high-speed capability detection during resume signaling

21 May 17, Timeline for Resume < 3.0 ms End of Resume Signaling Start of Resume Signaling HS Hub HS Device FS K HS idle μSOF D+ Device sees first activity Start of Resume Signaling D– FS idle > 20 ms Device Resumed < 1.33 μs

22 May 17, USB 2.0 High-Speed Eye Pattern Templates

23 May 17, Transmitter Eye Pattern Templates w These templates govern the output waveforms at various test planes w Waveforms are specified for a transmitter driving a reference test fixture w Waveforms do not specify actual signals observed on a USB link Vbus D+ D- Gnd Gnd 15.8 Ohms + To 50 Ohm Inputs of a High Speed Differential Oscilloscope, or 50 Ohm Outputs of a High Speed Differential Data Generator - 50 Ohm Coax “A” Plug N.C Ohms 143 Ohms 50 Ohm Coax

24 May 17, Three Transmitter Templates are Specified w At the pins of the transmitter (Tightest specification, guideline only) w At the connector nearest the transmitter (Only applies when there isn’t a captive cable) w At the “far end” of a captive cable (Loosest specification, applies when there is a captive cable) USB Cable Device Circuit Board Hub Circuit Board AConnectorAConnector TracesTracesTracesTraces TransceiverTransceiverTransceiverTransceiverTP4TP4TP3TP3TP2TP2TP1TP1BConnectorBConnector

25 May 17, Example of a “Passing” Transmitter Waveform w Note that higher level of overshoot is allowed in the unit interval following a transition

26 May 17, Failing Transmitter Waveform w Waveform is required to transition monotonically through range defined by the minimum eye opening

27 May 17, Failing Transmitter Waveform w Higher level of overshoot is only allowed in the unit interval following a transition

28 May 17, Narrow/Wide Symbols are Allowed as Long as they Conform to the Template

29 May 17, Receiver Sensitivity Templates w Receiver templates are never actually measured w These templates define the worst case allowable waveforms that a receiver is required to recover w Actual waveforms at specified planes will be better than the receiver templates

30 May 17, Three Receiver Templates are Specified w At the pins of the receiver (Tightest specification, guideline only) w At the connector nearest the receiver (Only applies when there isn’t a captive cable) w At the “far end” of a captive cable (Loosest specification, applies when there is a captive cable) w In compliance testing, worst case waveforms are generated with test equipment and applied through test fixture

31 May 17, How Is an Eye Pattern Measured? 1.The entire Test Packet waveform is captured with a single-shot transient capture instrument 2.The “best fit” frequency and delay are computed for the zero crossings in the record (bounded by the allowed frequency range of +/- 500 ppm) 3.The record is scanned for overshoot and monotonicity violations

32 May 17, How Is an Eye Pattern Measured? (cont.) 1.The unit intervals are “cut” and “superimposed” to produce the aggregate eye pattern 2.The aggregate pattern is examined for template violations


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