1. Ch.10 SoC Design TAIST ICTES Program VLSI Design Methodology Hiroaki Kunieda Tokyo Institute of Technology

2. System Design Behavior Description Behavior Partitioning Behavior Design （ Algorithm design ） Discrete Time 、 Quantization 、 Precision Power, Cost, Interface Structure Design Parallel/Pipeline Processing High Level Synthesis (Scheduling/Allocation) SW/HW, Processor 、 ASIC 、 ASIP, IP Optimal Realization for required System Performance High Level Synthesis

3. System Specification the clarification of any possible ambiguity the careful definition of the project scope approximated costs for development Identification of competition subsequent improvement on their capabilities

4. System Design Target Platform / Computation model ASIP, Processor with or without RTOS, ASIC, FPGA Fixed Point Arithmetic Multiplication/ Division Memory Pin Assignment

5. 10.1 Algorithm Design System Development Tool System Description Language Hardware Oriented Algorithm

6. a. System Development Tool MATLAB/SIMULINK MATLAB® is a high-level technical computing language and interactive environment for algorithm development, data visualization, data analysis, and numeric computation. Using the MATLAB product, you can solve technical computing problems faster than with traditional programming languages, such as C, C++, and Fortran. Control, DSP, Image Processing, Communication, Neural Network, Statics, Optimization, Differential Equations

7. Key Features High-level language for technical computing Development environment for managing code, files, and data Interactive tools for iterative exploration, design, and problem solving Mathematical functions for linear algebra, statistics, Fourier analysis, filtering, optimization, and numerical integration 2-D and 3-D graphics functions for visualizing data Tools for building custom graphical user interfaces Functions for integrating MATLAB based algorithms with external applications and languages, such as C, C++, Fortran, Java, COM, and Microsoft Excel

8. b. System Description Language #include "systemc.h“ SC_MODULE (up_down_counter) { //-----------input ports--------------- sc_in clk; sc_in reset; sc_in enable; sc_in up_down; //------------output ports--------------- sc_out > out; //------------internal variables-------- sc_uint count; //--------------process declaration------- void counter () { if (reset.read()) { count = 0 ; } else if (enable.read()) { if (up_down.read()) { count = count + 1;} else { count = count - 1; } } out.write(count); } //-------------process registration-------- SC_CTOR(up_down_counter) { SC_METHOD (counter); sensitive << clk.pos(); } }; Up-down Counter by SystemC

9. SystemC sc_prim_channel is the base class for all primitive channels, and provides such channels with unique access to the update phase of the scheduler. This standard provides a number of predefined primitive channels to model common communication mechanisms. Some of them are sc_mutex sc_fifo sc_semaphore

10. c. Hardware Oriented Algorithm Inner Product –Distributed Arithmetic- Hardware Algorithm for Inner Product DFT, DCT, Digital Filters Basic Idea Input data is decomposed into a group of bits. By replacing order of calculation in such a way that multiplication between coefficent and each bit is performed and accumulated at first and accumulate the results with shifting.

11. Bit Manupilation Inner Product Bit 2’s complement Representation of xn By substituting and changing an order of operations as, Realized by ROM with N-bits address and NBc-bits data

12. Inner Product Circuit

13. 8 point DCT Implementation

14. 10.2 Architecture Design a. High Level Synthesis b. ASIP Design c. FPGA Design

15. a. High Level Synthesis Scheduling : to decide the time and Op unit for each operation. Allocation: to decide registers or memory to store the data Output: Data path and its control logic circuit are derived. CDFG: Control and Data flow Graph is constructed. Software Language (C/C++, System C) simulation is available on PC.

16. Example: Directed acyclic graph

17. Example: Scheduling

18. Example: Binding(allocation)

19. Example: Final Data-Path

20. Example: Controller

21. Hardware Cost 1.Area or hardware 2.Delay or Speed 3.Power Critical path

22. Schedule Methods

23. b. ASIP Design with LISA

24. c. FPGA Design Functional Verification Logic Synthesis RTL Simulation RTL Synthesis Netlist Gate Assignment LE Place and Rout Configuration Data FPGA Tool LSI Tool

25. END

26. Systolic Algorithm

27. Alternative Method Systolic Array Low parallel Efficiency inefficient Data Memory Bottle Neck for I/O PE number uniquely decided Restricted to local communication between PEs Memory Sharing Processor Array （ MSPA) High parallel Efficiency Minimization of Data Memory Restriction to I/O ports Restriction to PE number Not restricted to local communication

28. MSPA Theory Find out appropriate cordinate Of Time and Space, which may Not violate the precedence Relation between operations.

29. Comparisons Size SystolicMSPA time #PE Parallel Efficiency time #PE Parallel Efficiency ４ 1910 ３４％３４ 2 ９４％ 10 １０９ 28 ３３％ 2085 ９６％ 501,71749 ３３％ 8,42518 ９８％ 20115,0011401 39 ％ 80,801101 100 ％ Matrix Product Case

30. Widow-MSPA I MSPA for Widow Operation Minimize I/O ports and decide #PE Fast Parallel Operation Flexible #PE and processing time Applicable various Image Processing such as motion vector search Window Image 出力

31. WINDOW-MSPA ARCHITECTURE WINDOW--MSPA Internal data parallel distribution network WPE Output Network Input Network External Image Data Memory External Output Data Memory Widow-MSPA II

32. ① PE00 でデータを 9 クロックで受信して処理（ 1 行目ポート１、－ －－） ② PE01 でデータを 9 クロックで受信して処理（①より 1 クロック遅 れる） ③ PE02 でデータを 9 クロックで受信して処理（②より 1 クロック遅 れる） ④ PE03 でデータを 9 クロックで受信して処理（③より 1 クロック遅 れる） ⑤ PE04 でデータを 9 クロックで受信して処理（④より 1 クロック遅 れる） ⑥ PE11 でデータを 9 クロックで受信して処理（①より 3 クロック遅 れる） ① ② ③ ④ ⑤ ⑥ ① ② ③ ④ ⑤ ⑥ ⑦ ⑧ ⑨ ⑩ Widow-MSPA 理論 3 （ 1996-1998 ）

33. Operation of Window-MSPA Clock 0123456789101112131415161718192021222324 Global/IO_0 (0,0)(0,1)(0,2)(0,3)(0,4)(0,5)(0,6) (3,0)(3,1)(3,2)(3,3)(3,4)(3,5)(3,6) (6,0)(6,1)(6,2)(6,3)(6,4)(6,5)(6,6) Global/IO_1 (1,0)(1,1)(1,2)(1,3)(1,4)(1,5)(1,6) (4,0)(4,1)(4,2)(4,3)(4,4)(4,5)(4,6) Global/IO_2 (2,0)(2,1)(2,2)(2,3)(2,4)(2,5)(2,6) (5,0)(5,1)(5,2)(5,3)(5,4)(5,5)(5,6) Local/IO.00 (0,0)(0,1)(0,2)(0,3)(0,4)(0,5)(0,6) (3,0)(3,1)(3,2)(3,3)(3,4)(3,5)(3,6) Local/IO.01 (1,0)(1,1)(1,2)(1,3)(1,4)(1,5)(1,6) (4,0)(4,1)(4,2)(4,3)(4,4)(4,5)(4,6) Local/IO.02 (2,0)(2,1)(2,2)(2,3)(2,4)(2,5)(2,6) (5,0)(5,1)(5,2)(5,3)(5,4)(5,5)(5,6) PE(0,0) PE(0,1)PE(0,2) Local/IO.10 (1,0)(1,1)(1,2)(1,3)(1,4)(1,5)(1,6) (4,0)(4,1)(4,2)(4,3)(4,4)(4,5)(4,6) Local/IO.11 (2,0)(2,1)(2,2)(2,3)(2,4)(2,5)(2,6) (5,0)(5,1)(5,2)(5,3)(5,4)(5,5)(5,6) Local/IO.12 (3,0)(3,1)(3,2)(3,3)(3,4)(3,5)(3,6) (6,0)(6,1)(6,2)(6,3)(6,4)(6,5)(6,6) PE(1,0)PE(1,1)PE(1,2) Local/IO.20 (2,0)(2,1)(2,2)(2,3)(2,4)(2,5)(2,6) Local/IO.21 (3,0)(3,1)(3,2)(3,3)(3,4)(3,5)(3,6) Local/IO.22 (4,0)(4,1)(4,2)(4,3)(4,4)(4,5)(4,6) PE(2,0)PE(2.1)PE(2,2)

34. Widow-MSPA 理論 1 （ 1996-1998 ） Widow サイズ シストリックアレイ Window-MSPA 処理時間 演算器数 （入力ポート数） 並列効率処理時間 演算器数 （入力ポート 数） 並列効率 ３ｘ３ 8099 （２） 49 ％ 6663 （９） 87 ％ ８ｘ８ 51464 （７） 44 ％ 176120 （３） 68 ％ １６ｘ１ ６ 354256 （ 15 ） 14 ％ 35249 （２） 73 ％ 画面サイズはいずれも２２ｘ２２

35. Example 1. Line Direction

36. Problem Description [Problem] Find out a 3x3 direction type, Which is included the most among Line pattern in target image. [Software Solution] To count the number of direction Types among the line pattern In the target image.

37. Hardware Solution 1. Describe a direction pattern by 9 bit signals such as (000111111) for the first direction type. 2. Use each direction pattern as 9 bit address data of ROM, whose data is a increment signal of corresponding accumulation registers. ROM Address 9 bits Data 24 bits Direction Type 0 Direction Type 1 Direction Type 2 Direction Type 23 Increment signals Select the largest number in the registers Direction of Line pattern