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ECOE 560 Design Methodologies and Tools for Software/Hardware Systems Spring 2004 Serdar Taşıran.

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Presentation on theme: "ECOE 560 Design Methodologies and Tools for Software/Hardware Systems Spring 2004 Serdar Taşıran."— Presentation transcript:

1 ECOE 560 Design Methodologies and Tools for Software/Hardware Systems Spring 2004 Serdar Taşıran

2 ECOE 560, Spring 2004 2 Stepwise refinement At each level of abstraction, we must: analyze the design to determine characteristics of the current state of the design; refine the design to add detail. Design: specify and enter the design intent Implement : refine the design through all phases Verify: verify the correctness of design and implementation

3 ECOE 560, Spring 2004 3 Successive refinement model specify architect design build test initial system specify architect design build test refined system

4 ECOE 560, Spring 2004 4 Hardware/software design flow requirements and specification architecture hardware design software design integration testing

5 ECOE 560, Spring 2004 5 Hierarchical HW/SW flow spec architecture HWSW integrate test system spec HW architecture detailed design integration test hardware spec SW architecture detailed design integration test software

6 ECOE 560, Spring 2004 6

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8 8 Outline of today’s lecture What is a software/hardware (embedded) system? Course outline Design automation methodologies and tools Levels of abstraction in design descriptions

9 ECOE 560, Spring 2004 9 Levels of Abstraction: Hardware System level Register-transfer level (RTL) Gate level Transistor level Layout level

10 ECOE 560, Spring 2004 10

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15 ECOE 560, Spring 2004 15 Levels of Abstraction: Software Specification: Behavioral (UML diagrams, statecharts, algorithm pseudocode) Architecture: Structural (UML), SystemC Implementation: High-level language Assembly Executable (binary)

16 16 Data flow graph x = a + b; y = c - d; z = x * y; y1 = b + d; single assignment form + - +* DFG a bc d z x y y1

17 17 Control-data flow graph CDFG: represents control and data. Uses data flow graphs as components. Two types of nodes: decision; data flow.

18 18 CDFG example if (cond1) bb1(); else bb2(); bb3(); switch (test1) { case c1: bb4(); break; case c2: bb5(); break; case c3: bb6(); break; } cond1 bb1() bb2() bb3() bb4() test1 bb5()bb6() T F c1 c2 c3

19 ECOE 560, Spring 2004 19 Course Outline System design flow Modeling, specifying, and representing systems: Description languages for design specifications and implementations Modeling formalisms: Models of computation and concurrency Fundamentals: Boolean algebras, functions, relations. Propositional logic, first-order logic. Temporal logics. Hardware implementation (component) technologies: CPUs, ASICs, FPGAs, DSPs, IP blocks, I/O components, networks, buses, on-chip communication networks, reconfigurable platforms. Software implementation (component) technologies: Operating systems, real-time operating systems, inter-process communication, scheduling. Analysis, verification, testing: Functionality. Design and implementation verification. Simulation, emulation, formal verification. Analysis, verification, testing: Performance and timing. Timing analysis and verification of hardware and software. Performance evaluation and estimation. Analysis, verification, testing: Power. Power analysis, optimization of hardware and software. Power minimization techniques. System partitioning, architecture exploration. Hardware synthesis. Software synthesis Interface design and synthesis


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