Ch.6 Logic Verification Standard Cell Design TAIST ICTES Program VLSI Design Methodology Hiroaki Kunieda Tokyo Institute of Technology.

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Ch.6 Logic Verification Standard Cell Design TAIST ICTES Program VLSI Design Methodology Hiroaki Kunieda Tokyo Institute of Technology

Design Verification How to confirm the correctness of design result 50-70% of design period is used for design verification. Methods Logic Simulation and Emulation Formal Verification

Logic Design Functional Verification Logic Synthesis Scan Path Design RTL Simulation RTL Synthesis Netlist Scan Netlist Timing Analysis Functional Verification

6.1 Logic Simulation

Logic Design 1 HDL Simulation [Objective] to correct HDL description by simulating its performance and checking its timing due to delays of logic circuit. [Method] 1. HDL/Logic Simulator

01xz 00000 101xx x0xxx z0xxx Truth Table of AND Gate Logic Design 1 Four Valued Logic Not only 0 and 1, but other values such as UNKNOWN X, HIGH IMPEDANCE Z are used for the simulation. Their response are described by truth table.

Simulation Method 1. Event Driven Simulation Outputs of the gates has been evaluated by truth table, only when an event occurs on inputs of the gates. Since small portion of whole circuit works at a time, this scheme avoid waste computation. Thus, simulator keeps track of those events. 2. Time wheel Event Table Change of outputs of the gates are stored as an event. That event occurs delayed at component delay after event of inputs occurs. The time of next events are stored in event table. The table is considered to be wheel so that it can store events of all simulation periods, efficiently.

Event Driven Event is a change of logic value. The event entered into a gate may generate another event at the output of the gate after the gate delay time. Event of Signals propagates through Logic circuits. Event Driven Analysis is to update Logic values only when events occur at the wire so as to minimize computational complexity. 30% or less logic parts is running at the same time.

Logic Simulation Example

6.2 Formal Verification

Formal Verification Functional Verification Logic Synthesis Scan Path Design RTL Simulation RTL Synthesis Netlist Scan Netlist Timing Analysis Functional Verification

Logic Design 3 Formal Verification [Objective] to confirm coincidence between HDL description and designed logic circuit. Simulation uses various test inputs, while formal verification uses equivalence of two functions. [Method] BDD method (Binary Decision Diagram) It is effective way to show equivalent representation of logic functions for two targets. [Problem] 1. Reduction of scan path flip flops 2. Speed up of testing such as concurrent testing

Logic Design 3 BDD Representation 1 1 0 1 1 11 1 1 0 000 0 0 BDD representation will be unique according to the best variable order. There was heuristic algorithm to derive the reduced BDD from original.

BDD Operation (1) Merge of 2 isomorphic subgraphs

BDD Operation (1) Merge of 2 isomorphic subgraphs

BDD Operation (2) Eliminate node, whose son nodes are isomorphic.

BDD Operation (2)

Order of nodes X3X3 X5X5 X5X5 X2X2 X2X2 X2X2 X2X2 X3X3 X5X5 X5X5 X4X4 X4X4 X6X6 X1X1 1 0 Ｗｏｒｓｔ Ｂｅｓｔ X1 X2 X3 X4 X5 X6 X5X5 X2X2 X3X3 X4X4 X6X6 X1X1 10

Optimal Order Search i-1 i i+1 i 01 (A) (B) (C) (D) i i-1 i+1 i-1 i+1 01 (A) (C)(B) (D) i-1 i i 0 1 f1 f2 f3 i i-1 01 f1f2f3

Verification example I ab ｑ1ｑ1 q0 ｄ1ｄ1 ｄ0ｄ0 000000 010001 100000 110001 000100 010111 100100 110110 001010 011011 101010 111010 001110 011110 101100 111110 ｄ 0=bq 1 ’q 0 ’+a’bq 1 ’+a’ ｂ q 0 ’ d1=q 1 q 0 ’+a’q 1 + ｂ q 0

Verification example II F1=q0’ ・ a’ q0’ a’ q1’ F2=(q0’+a’)q1‘ q0’+a’ (F1+F2)’ F1=q0’ ・ a’ の 補正のため 葉の 0 と１を 交換

Verification example III ｄ0=bq 1 ’q 0 ’+a’bq 1 ’+a’ｂq 0 ’

6.3 Timing Analysis

Timing Analysis Timing Analysis is to check the timing violation of logic circuits, due to gate delays and wire delays. In order to reduce computation, critical paths analysis is done by using graph representation. Pre Layout timing analysis: Only gate delay is considered. Post Layout timing analysis: Gate delay and wire delay are considered. The latter delays are decided by layout pattern. This analysis is only performed after layout design.

Timing Analysis ․ Calculate timing of synthesized netlist Make sure circuit operates correctly under specified timing constraints ․ Static Timing Analysis (STA) Timing analysis without input patterns － Fast but not accurate Used after logic synthesis ․ Dynamic Timing Analysis Timing analysis with input patterns Slow but accurate Used after physical design with few patterns

Timing Analysis identifies critical path with graph model, instead of exhausted search with logic simulator. Logic Design 5 Timing Analysis (Pre) nodes １２３４５６７８９１０１０ 1 50 2 62 506088 3 50 62 50100 4 50 62 50100 112

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