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**EKT 124 / 3 DIGITAL ELEKTRONIC 1**

CHAPTER 3 Counters (cont.)

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Example: Design a counter with the irregular binary count sequence 1,2,5,7,1,…..as shown in the state diagram. Use J-K flip-flops. 1. State Diagram

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2. Next-state table Present State Next State Q2 Q1 Q0 1

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**Transition Table for a J-K flip-flop**

Output Transitions Flip-flop Inputs QN QN+1 J K X 1

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3.K-Map

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4.The Counter Circuit

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**Example: State diagram for a 3-bit up/down Gray code counter.**

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**The 74HC163 4-bit synchronous binary counter**

The 74HC163 4-bit synchronous binary counter. (The qualifying label CTR DIV 16 indicates a counter with sixteen states.)

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Timing example for a 74HC163.

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**The 74LS160 synchronous BCD decade counter**

The 74LS160 synchronous BCD decade counter. (The qualifying label CTR DIV 10 indicates a counter with ten states.)

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Timing example for a 74LS160.

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**UP/DOWN SYNCHRONOUS COUNTER A basic 3-bit up/down synchronous counter.**

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Timing Diagram

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**The 74HC190 up/down synchronous decade counter.**

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Timing example for a 74HC190.

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**J and K maps - The UP/DOWN control input, Y, is treated as a fourth variable.**

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**Three-bit up/down Gray code counter**

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