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CHAPTER 3 Counters (cont.). Example: Design a counter with the irregular binary count sequence 1,2,5,7,1,…..as shown in the state diagram. Use J-K flip-

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Presentation on theme: "CHAPTER 3 Counters (cont.). Example: Design a counter with the irregular binary count sequence 1,2,5,7,1,…..as shown in the state diagram. Use J-K flip-"— Presentation transcript:

1 CHAPTER 3 Counters (cont.)

2 Example: Design a counter with the irregular binary count sequence 1,2,5,7,1,…..as shown in the state diagram. Use J-K flip- flops. 1. State Diagram

3 2. Next-state table Present State Next State Q2Q2 Q1Q1 Q0Q0 Q2Q2 Q1Q1 Q0Q

4 Transition Table for a J-K flip-flop Output TransitionsFlip-flop Inputs QNQN Q N+1 JK 0  00X 0  11X 1  0X1 1  1X0

5 3.K-Map

6 4.The Counter Circuit

7 Example: State diagram for a 3-bit up/down Gray code counter.

8 The 74HC163 4-bit synchronous binary counter. (The qualifying label CTR DIV 16 indicates a counter with sixteen states.)

9 Timing example for a 74HC163.

10 The 74LS160 synchronous BCD decade counter. (The qualifying label CTR DIV 10 indicates a counter with ten states.)

11 Timing example for a 74LS160.

12 UP/DOWN SYNCHRONOUS COUNTER A basic 3-bit up/down synchronous counter.

13 Timing Diagram

14 The 74HC190 up/down synchronous decade counter.

15 Timing example for a 74HC190.

16 J and K maps - The UP/DOWN control input, Y, is treated as a fourth variable.

17 Three-bit up/down Gray code counter


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