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Multi-Bit Upsets in the Virtex Devices Heather Quinn, Paul Graham, Jim Krone, Michael Caffrey Los Alamos National Laboratory Gary Swift, Jeff George, Fayez.

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Presentation on theme: "Multi-Bit Upsets in the Virtex Devices Heather Quinn, Paul Graham, Jim Krone, Michael Caffrey Los Alamos National Laboratory Gary Swift, Jeff George, Fayez."— Presentation transcript:

1 Multi-Bit Upsets in the Virtex Devices Heather Quinn, Paul Graham, Jim Krone, Michael Caffrey Los Alamos National Laboratory Gary Swift, Jeff George, Fayez Chayab XRTC

2 Multi-Bit Upsets Multiple neighboring bits flipped from a single ionized particle strike Common to all memory devices FPGAs a unique case – Heterogeneous layout affects the size, shape – Domain crossing event (DCE) where an SEU affects two or more TMR modules are a concern

3 MBU Research Plan Determine the event rate Determine the MBU frequency – Multiple families of FPGAs: feature size, epi – Radiation type: proton and heavy ion – Strike angle Determine the DCEs frequency – Early simulation results – Early probabilistic model to predict DCEs

4 Virtex Proton Test Setup: Crocker Nuclear Laboratory, UC-Davis SLAAC1-V Linux PC Proton Source

5 LANL V2 and V4 Hardware Test Fixture Virtex-II AFX Board USB 2.0 Interface to Linux PC Virtex-4 AFX Board

6 LANL Software Test Fixture Text-based interface – SSH'd into the test machine – Instant access to incremental readback results Tight readback/scrubs cycle – Saves differential bitstream for upsets – Saves FAR, COR, and STAT registers – Cycles approximately once a second – Scrubs entire bitstream Data analyzed for MBUs post-collection

7 Data Collection & Analysis ● Possibility of coincident SBUs must be minimized ● Minimize the number of upsets per readback ● Fluence per readback cycle controlled ● SEFIs (or unexplained events) removed in post-collection data analysis procedures ● SEFIs present as numerous large MBUs: skew statistics ● Data cube insignificantly reduced, results cleaner

8 Heavy Ion Accelerator Tests Done by Xilinx Radiation Testing Consortium Collected data for:

9 Heavy Ion Event Bit Cross-Sections

10 V4 Heavy Ion Event and Upsets Cross-Sections 63 % decrease in cross- sections

11 Percentage of MBU Events in Heavy Ion: Comparison Across Families

12 V4 Percentage of Events by Resource: BRAM, CLB

13 V4 MBUs from Angle Strikes Across Columns

14 V4 MBUs from Angle Strikes Down Columns

15 Proton Accelerator Tests Done by Los Alamos National Laboratory Collected data for:

16 Percentage of MBU Events in Proton at 63 MeV: Comparison Across Families

17 Proton Bit-Cross-Sections

18 V4 Proton Event and Upsets Cross-Sections 9 % decrease in cross-sections

19 MBUs from Angle Strikes Down Columns

20 TMR Studies TMR designs: – Edge detection, max filter, min filter – Each design has 2-3 implementations that vary module granularity LANL/BYU SEU simulation extended to simulate column MBUs: – Observe, characterize, and determine the DCE rate – Test both 1-bit and 2-bit column events Data inconclusive at best

21 TMR Results: MBU Sensitive Bits Device: XC2V250 (Virtex-II) with 1.6 Million Bits Even without triplicated clocks, TMR improves the cross-section 4-6 times

22 Given an MBU what is the probability of a DCE? SBUsMBUs BRAM CLB BRAMi IOB BRA MCLB BRAMiIOB Voted Out Voted Out DCEDCE Need to determine what percentage of the event space are DCEs

23 Probability of an MBU DCE in CLBs and BRAMi: Proton-Induced Radiation Events

24 Probability of a DCE in CLBs and BRAMi: Heavy-Ion-Induced Radiation Events

25 Summary MBU problem getting worse with each generation DCEs in TMR a concern Need more data collection, more simulation, more modeling – Data collection: finish qualification – Simulation: complete TMR studies with more designs and more devices – Modeling: predict on-orbit SBU/MBU rates


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