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TMR Schemes Melanie Berg MEI Technologies/NASA GSFC

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Presentation on theme: "TMR Schemes Melanie Berg MEI Technologies/NASA GSFC"— Presentation transcript:

1 TMR Schemes Melanie Berg MEI Technologies/NASA GSFC

2 Page 2 European Space Agency FPGA Tool Workshop. Noordwijk, NL; Melanie Berg Overview Premise: Why do various FPGAs require separate mitigation strategies? Radiation Effects in FPGA devices Mitigation and Actel Anti-fuse Devices Mitigation and Xilinx Virtex Devices Tools

3 Page 3 European Space Agency FPGA Tool Workshop. Noordwijk, NL; Melanie Berg Radiation Effects in FPGA devices Single Event Transients (SETs) Single Event Upsets (SEUs) Single Event Functional Interrupts (SEFIs)

4 Page 4 European Space Agency FPGA Tool Workshop. Noordwijk, NL; Melanie Berg Single Event Effects (SEEs) and IC System Error SEUs or SETs can occur in: Combinatorial Logic Sequential Logic Configuration Memory Cells Depending on the Device and the design, each fault type will: Have a probability of occurrence Either have a significant or insignificant contribution to system error Every Device has different Error Responses – We must understand the differences and design appropriately

5 Page 5 European Space Agency FPGA Tool Workshop. Noordwijk, NL; Melanie Berg Combinatorial Logic Blocks and Potential Upsets… SETs in Anti-fuse FPGAs

6 Page 6 European Space Agency FPGA Tool Workshop. Noordwijk, NL; Melanie Berg Basic Combinatorial Logic Blocks and Potential Upsets TRANSIENT P SET STUCK UNTIL OVERWRITTEN Probability of Configuration Fault P Configuration

7 Page 7 European Space Agency FPGA Tool Workshop. Noordwijk, NL; Melanie Berg DFFs: SEUs and SEFIs Strike Caught in Loop D Q reset CLK P DFFSEU Probability of SEU Probability of SEFI P SEFI

8 Page 8 European Space Agency FPGA Tool Workshop. Noordwijk, NL; Melanie Berg Transient Capture on A DFF Data Input Pin (SETSEU) clock T pulse t p = 1/f s P( fs ) SETSEU fs : System Frequency T(fs) pulse : SET Pulse Width P(fs) SETgen : Probability SET generated with sufficient amplitude P(fs) SETprop : Probability SET can propagate with sufficient amplitude P DFFEn : Probability DFF is enabled (active) P(fs) SETSEU : Probability SET can be caught by clock edge

9 Page 9 European Space Agency FPGA Tool Workshop. Noordwijk, NL; Melanie Berg Frequency Effects and Conventional DFF Upset Theory DFFerror Frequency Composite Cross Section ~0 P DFFSEU & P DFFMBU P( fs ) SETSEU P DFF ( fs ) error

10 Page 10 European Space Agency FPGA Tool Workshop. Noordwijk, NL; Melanie Berg Summary: Most Significant Factors of System Error Probability P( fs ) error ConfigurationDFFsSEFIs SRAM Based FPGAs STATIC SEU Dynamic SETSEU Clocks & Resets Inaccessible control circuitry

11 Page 11 European Space Agency FPGA Tool Workshop. Noordwijk, NL; Melanie Berg Reducing System Error: Common Mitigation Techniques Mitigation can be: Embedded: built into the device library cells User does not verify the mitigation – manufacturer does User inserted: part of the actual design process User must verify mitigation… Complexity is a RISK!!!!!!!! Common Mitigation Types: Local Triple Modular Redundancy (LTMR) Global Triple Modular Redundancy (GTMR)

12 Page 12 European Space Agency FPGA Tool Workshop. Noordwijk, NL; Melanie Berg Example Mitigation Schemes will use Majority Voting I0I1I2 Majority Voter

13 Page 13 European Space Agency FPGA Tool Workshop. Noordwijk, NL; Melanie Berg Mitigation and Actel Anti- fuse Devices

14 Page 14 European Space Agency FPGA Tool Workshop. Noordwijk, NL; Melanie Berg ACTEL RTAX-S Architecture Basics Embedded RHBD: Hardened Global Clocks and Resets Antifuse Configuration is SEU immune Embedded Localized TMR (LTMR) at each DFF (RCELL) Source: RTAX-S/SL RadTolerant FPGAs 2009 Actel.com Super Cluster: Combinatorial Cells: C CELLS DFF Cells: R Cells

15 Page 15 European Space Agency FPGA Tool Workshop. Noordwijk, NL; Melanie Berg Local Triple Modular Redundancy (LTMR): Smallest Area & Power Triple Each DFF + Vote… Data paths are not redundant – can only have one voter Unprotected: Clocks and Resets… SEFI Transients (SET->SEU) Internal/hidden device logic: SEFI Low Non-MitigatedMitigated

16 Page 16 European Space Agency FPGA Tool Workshop. Noordwijk, NL; Melanie Berg ACTEL RTAX-S Embedded Mitigation… LTMR and SETs Combinatorial logic: C-CELL Sequential logic R-CELLCombinatorial logic C-CELL XXXXXX Super Cluster CR RX TX RX TX RX TX RX TX B CCCR Combinatorial logic C-CELL TX C C C R RX

17 Page 17 European Space Agency FPGA Tool Workshop. Noordwijk, NL; Melanie Berg RTAX Example: Probability of Error Reduction Error Probability is Per DFF bit Error Rate must reflect frequency of operation Low ~0 0

18 Page 18 European Space Agency FPGA Tool Workshop. Noordwijk, NL; Melanie Berg Upper-Bound Error Prediction RHBD Anti-fuse FPGA DFF (near) Static Error Bit Rate no CCells P DFFSEU : 15MHz to 120MHz: Dynamic Error Bit Rate with 8 levels of CCells P( fs ) SETSEU : Source: Actel Source: NASA Goddard

19 Page 19 European Space Agency FPGA Tool Workshop. Noordwijk, NL; Melanie Berg Upper-Bound Error Prediction Actel RHBD Anti-fuse FPGA With embedded LTMR Mitigation + Hardened Clocks: Thousands of years in LEO !!!!!

20 Page 20 European Space Agency FPGA Tool Workshop. Noordwijk, NL; Melanie Berg Mitigation and Xilinx Virtex Devices

21 Page 21 European Space Agency FPGA Tool Workshop. Noordwijk, NL; Melanie Berg Xilinx XQR4VSX55: Radiation Test Data For non-mitigated designs the most significant upset factor is: Xilinx Consortium: VIRTEX-4VQ STATIC SEU CHARACTERIZATION SUMMARY: April/2008 ProbabilityError RateLEOGEO Configuration Memory: XQR4VSX55 P configuration Combined SEFIs per device P SEFI 7.5x x10 -5 M Berg, Trading ASIC and FPGA Considerations for System Insertion; IEEE Nuclear Science Radiation Effects Conference 2009

22 Page 22 European Space Agency FPGA Tool Workshop. Noordwijk, NL; Melanie Berg Global Triple Modular Redundancy (GTMR): Largest Area Greatest Complexity Triple Entire Design Triple I/O and Voters Unprotected – hidden device logic SEFIs Can not be an embedded strategy: Complex to verify Xilinx offers XTMR Low Non-Mitigated Mitigated Low

23 Page 23 European Space Agency FPGA Tool Workshop. Noordwijk, NL; Melanie Berg XTMR – Capturing Asynchronous Input data INPUT SKEW EDGE DETECT TIMING WAVEFORM Async_data_tr0 Async_data_tr1 Async_data_tr2 Dynamic Analysis : One domain leads the other two

24 Page 24 European Space Agency FPGA Tool Workshop. Noordwijk, NL; Melanie Berg Time Domain Considerations: XTMR Single Bit Failures …Not Detected by Static Node Analysis CONFIGURATION BIT HIT NO EDGE DETECTION

25 Page 25 European Space Agency FPGA Tool Workshop. Noordwijk, NL; Melanie Berg Voters and Asynchronous Signal Capture VOTERVOTER Place voter after metastability filters It satisfies skew constraints because voter is anchored at DFF control points

26 Page 26 European Space Agency FPGA Tool Workshop. Noordwijk, NL; Melanie Berg P Configuration ??? SEUs are insignificant MBUs may be insignificant (still under investigation) Assumes proper scrubbing Upper-Bound Error Prediction: Xilinx FPGA XTMR Assumes Unmitigated SEFIs are the most predominant source:

27 Page 27 European Space Agency FPGA Tool Workshop. Noordwijk, NL; Melanie Berg Tools

28 Page 28 European Space Agency FPGA Tool Workshop. Noordwijk, NL; Melanie Berg Mitigation and Actel Tools Mentor Graphics has offered LTMR for anti-fuse devices There is a desire to employ LTMR to Actel Flash Based products DTMR is another approach (GTMR with no clock redundancy) Flash Assist with SETs in Anti-fuse Device

29 Page 29 European Space Agency FPGA Tool Workshop. Noordwijk, NL; Melanie Berg Mitigation and Xilinx Tools Currently XTMR is commercially available from Xilinx NASA REAG has identified some issues: Asynchronous domain crossings Verification of XTMR insertion Mentor is now evaluating GTMR with Formal Checking NASA REAG is expecting to use Mentor GTMR (preliminary version) for V5 radiation testing


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