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Figure 4.1. The function f (x 1, x 2, x 3 ) =  m(0, 2, 4, 5, 6).

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Presentation on theme: "Figure 4.1. The function f (x 1, x 2, x 3 ) =  m(0, 2, 4, 5, 6)."— Presentation transcript:

1 Figure 4.1. The function f (x 1, x 2, x 3 ) =  m(0, 2, 4, 5, 6).

2 x 2 (a) Truth table(b) Karnaugh map 0 1 01 m 0 m 2 m 3 m 1 x 1 x 2 00 01 10 11 m 0 m 1 m 3 m 2 x 1 Figure 4.2. Location of two-variable minterms.

3 Figure 4.3. A simple logic function. 1

4 Figure 4.4. Location of three-variable minterms.

5 Figure 4.5. Examples of three-variable Karnaugh maps. fx 1 x 3 x 2 x 3 += x 1 x 2 x 3 00 10 11 01 x 1 x 2 x 3 11 00 11 01 (a) The function of Figure 2.18 fx 3 x 1 x 2 += (b) The function of Figure 4.1 00011110 0 1 00011110 0 1

6 Figure 4.6. A four-variable Karnaugh map.

7 Figure 4.7. Examples of four-variable maps.

8 Figure 4.8. A five-variable Karnaugh map.

9 Figure 4.9. Three-variable function f =  m(0, 1, 2, 3, 7).

10 Figure 4.10. Four-variable function f =  m(2, 3, 5, 6, 7, 10, 11, 13, 14).

11 Figure 4.11. The function f =  m(0, 4, 8, 10, 11, 12, 13, 15).

12 Figure 4.12. The function f =  m(0, 2, 4, 5, 10, 11, 13, 15). x 1 x 2 x 3 x 4 00011110 1 1 1 1 1 1 00 01 11 101 1 x 1 x 3 x 4 x 2 x 3 x 4 x 2 x 3 x 4 x 1 x 3 x 4 x 1 x 2 x 4 x 1 x 2 x 4 x 1 x 2 x 3 x 1 x 2 x 3.

13 Figure 4.13. POS minimization of f =  M(4, 5, 6).

14 Figure 4.14. POS minimization of f =  M(0, 1, 4, 8, 9, 12, 15). x 1 x 2 x 3 x 4 0 00011110 000 0110 1101 1111 00 01 11 10 x 2 x 3 +  x 3 x 4 +  x 1 x 2 x 3 x 4 +++ 

15 Figure 4.15. Two implementations of f =  m(2, 4, 5, 6, 10) + D(12, 13, 14, 15). x 1 x 2 x 3 x 4 0 00011110 1d0 01d0 00d0 11d1 00 01 11 10 x 2 x 3 +  x 3 x 4 +  x 1 x 2 x 3 x 4 0 00011110 1d0 01d0 00d0 11d1 00 01 11 10 x 2 x 3 x 3 x 4 (a) SOP implementation (b) POS implementation

16 Figure 4.16. An example of multiple-output synthesis. x 1 x 2 x 3 x 4 00011110 11 11 111 11 00 01 11 10 x 1 x 2 x 3 x 4 00011110 11 11 11 11 00 01 11 10 (a) Function (b) Function 1 f 1 f 2 f 1 f 2 x 2 x 3 x 4 x 1 x 3 x 1 x 3 x 2 x 3 x 4 (c) Combined circuit for f 1 f 2 and

17 Figure 4.17. An example of multiple-output synthesis. Please see “portrait orientation” PowerPoint file for Chapter 4

18 Figure 4.18. Implementation in a CPLD.

19 Figure 4.19. Implementation in an FPGA.

20 Figure 4.20. Using 4-input AND gates to realize a 7-input product term. 7 inputs

21 Figure 4.21. A factored circuit. x 6 x 4 x 1 x 5 x 2 x 3 x 2 x 3 x 5

22 Figure 4.22. A multilevel circuit. x 1 x 2 x 3 x 4 f 1 f 2

23 Figure 4.23. A multilevel circuit. x 1 x 2 x 3 x 4 f g

24 Figure 4.24. The structure of a decomposition. 1 x 2 x 3 x 4 f g h x x 1 x 2 x 3 x 4 f g

25 Figure 4.25. An example of decomposition. Please see “portrait orientation” PowerPoint file for Chapter 4

26 Figure 4.26a. Implementation of XOR. x 2 x 1 x 1 x 2  x 2 x 1 x 1 x 2  (a) Sum-of-products implementation (b) NAND gate implementation

27 x 2 x 1 g x 1 x 2  (c) Optimal NAND gate implementation Figure 4.26b. Implementation of XOR. f = x 1  x 2 = x 1 x 2 + x 1 x 2 = x 1 (x 1 + x 2 ) + x 2 (x 1 + x 2 )

28 Figure 4.27. Conversion to a NAND-gate circuit. Please see “portrait orientation” PowerPoint file for Chapter 4

29 Figure 4.28. Conversion to a NOR-gate circuit. Please see “portrait orientation” PowerPoint file for Chapter 4

30 Figure 4.29. Circuit for Example 4.10.

31 x 1 x 2 x 5 x 4 f x 3 P 1 P 4 P 5 P 6 P 8 P 2 P 3 P 9 P 10 P 7 Figure 4.30. Circuit for Example 4.11.

32 x 1 x 2 x 3 x 4 x 5 f P 1 P 2 P 3 x 1 x 2 x 4 f x 5 (c) Circuit with AND and OR gates (a) NAND-gate circuit x 3 Figure 4.31. Circuit for Example 4.12. x 1 x 2 x 3 x 4 x 5 f (b) Moving bubbles to convert to ANDs and ORs

33 Figure 4.32. Circuit for Example 4.13. 2

34 Figure 4.33. Representation of f (x 1, x 2 ) =  m(1, 2, 3). x 1 0 0 1 1 0 1 0 1 f 0 1 1 1 01 00 11 10 x 2 x 1 x1 1x x 2

35 Figure 4.34. Representation of f (x 1, x 2, x 3 ) =  m(0, 2, 4, 5, 6).

36 Figure 4.35. Representation of f =  m(0, 2, 3, 6, 7, 8, 10, 15).

37 Figure 4.36. Generation of prime implicants for

38 Figure 4.37. Selection of a cover. Please see “portrait orientation” PowerPoint file for Chapter 4

39 Figure 4.38. Generation of prime implicants for

40 Figure 4.39. Selection of a cover. Please see “portrait orientation” PowerPoint file for Chapter 4

41 Figure 4.40. Selection of a cover for the function in Example 4.15. Please see “portrait orientation” PowerPoint file for Chapter 4

42 Figure 4.41. The coordinate *-operation. o o 0 0 11 1 0 x 1 0 x B i A i 0 1 x A i B i *

43 Figure 4.42. The coordinate #-operation. o 0 1 1 0 x B i A i 0 1 x A i B i #     o

44 Figure 4.43. An example four-variable function. 1 x 2 x 3 x 4 00011110 1 111 11 00 01 11 10 x 1 x 2 x 3 x 4 00011110 d1 1 d d 11 00 01 11 10 1 x 5 0=x 5 1= d x

45 Figure 4.44. Verilog code for the function in Figure 4.5a. module func1 (x1, x2, x3, f); input x1, x2, x3; output f; assign f = (~x1 & ~x2 & x3) | (x1 & ~x2 & ~x3) | (x1 & ~x2 & x3) | (x1 & x2 & ~x3) ; endmodule

46 Figure 4.45. Logic synthesis options in MAX+plusII.

47 Figure 4.46. Results of physical design.

48 Figure 4.47. Timing simulation results. (a) Timing in an FPGA (b) Timing in a CPLD

49 Figure 4.48. A complete CAD system. Please see “portrait orientation” PowerPoint file for Chapter 4

50 module example4_21 (x1, x2, x3, f); input x1, x2, x3; output f; assign f = (~x1 & ~x2 & ~x3) | (~x1 & x2 & ~x3) | (x1 & ~x2 & ~x3) | (x1 & ~x2 & x3) | (x1 & x2 & ~x3); endmodule Figure 4.49. Verilog code for the function in Figure 4.1.

51 Figure 4.50. Implementation of the Verilog code in Figure 4.49. DQ PAL-like block (from interconnection wires) x 1 x 2 x 3 unused 0 0 1

52 DQ PAL-like block (from interconnection wires) x 1 x 2 x 3 unused 0 1 Figure 4.51. Implementation using XOR synthesis (f = x 3  x 1 x 2 x 3 ).

53 Figure 4.52. Verilog code in Figure 4.49 implemented in a LUT.

54 module example4_22 (x1, x2, x3, x4, f); input x1, x2, x3, x4; output f; assign f = (~x1 & ~x2 & x3 & ~x4) | (~x1 & ~x2 & x3 & x4) | (x1 & ~x2 & ~x3 & x4) | (x1 & ~x2 & x3 & ~x4) | (x1 & ~x2 & x3 & x4) | (x1 & x2 & ~x3 & x4) ; endmodule Figure 4.53. Verilog code for f 1 in Figure 4.7.

55 module example4_23 (x1, x2, x3, x4, x5, x6, x7, f); input x1, x2, x3, x4, x5, x6, x7; output f; assign f = (x1 & x3 & ~x6) | (x1 & x4 & x5 & ~x6) | (x2 & x3 & x7) | (x2 & x4 & x5 & x7) ; endmodule Figure 4.54. Verilog code for the function of section 4.6.

56 Figure 4.55. Two implementations of a 7-variable function. x 6 x 4 f x 5 0 x 7 x 2 x 3 x 2 x 7 x 4 x 5 0 x 6 x 1 x 3 x 1 x 4 x 5 x 6 x 1 x 3 x 6 x 2 x 3 x 7 x 2 x 4 x 5 x 7 (a) Sum-of-products realization x 1 x 7 x 2 x 6 x 1 x 6 x 2 x 7 + x 5 x 3 x 4 f (b) Factored realization x 1

57 Figure P4.1. Expansion of implicant x 1 x 2 x 3. x 2 x 3 x 1 x 3 x 1 x 2 x 3 x 2 x 3 x 1 x 2 x 1 x 1 x 2 x 3 NO

58 Figure P4.2. Circuit for problem 4.33.

59 Figure P4.3. Circuit for problem 4.34.


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