ECE 260B – CSE 241A Manufacturing 3http://vlsicad.ucsd.edu Basic Fabrication: Two Steps (1) Transfer an image of the design to the wafer (2) Using that image as a guide, create the desired layer on silicon l diffusion (add impurities to the silicon) l oxide (create an insulating layer) l metal (create a wire layer) Use the same basic mechanism, photolithography, to do (1) Use three different methods to do (2) l Ion implant - used for diffusion: Shoot impurities at the silicon l Deposition - used for oxide/metal: Usually chemical vapor (CVD) l Grow - used for some oxides: Place silicon in oxidizing ambient Courtesy K. Yang, UCLA
ECE 260B – CSE 241A Manufacturing 4http://vlsicad.ucsd.edu Photolithography Repeat: l Create a layer on the wafer (either before (oxide, metal) or after (diffusion) resist) l Put a photo-sensitive resist on top of the wafer l Optically project an image of the pattern you desire on the wafer l Develop the resist l Use the resist as a mask to prevent the etch (or other process) from reaching the layer under the resist, transferring the pattern to the layer l Remove the resist All die on the wafer are processed in parallel, and for some chemical steps, many wafers are processed in parallel Courtesy K. Yang, UCLA
ECE 260B – CSE 241A Manufacturing 5http://vlsicad.ucsd.edu Photolithography Start with wafer at current step Spin on a photoresist Pattern photoresist with mask Step specific processing etch, implant, etc... Wash off resist Courtesy K. Yang, UCLA
ECE 260B – CSE 241A Manufacturing 6http://vlsicad.ucsd.edu Photoresist Types Positive resists l material is removed from exposed areas during development l most widely used Negative resists l material is removed from unexposed areas during development l less mature Mask Resist Silicon Post development profile for positive and negative photoresists
ECE 260B – CSE 241A Manufacturing 7http://vlsicad.ucsd.edu Mask Types Bright field masks l opaque features defined by chrome l background is transparent l used, e.g., for poly and metal Dark field masks l transparent features defined l background is opaque (chrome) l used, e.g., for contacts l used also for damascene metals Clear areas Opaque (chrome) areas
ECE 260B – CSE 241A Manufacturing 8http://vlsicad.ucsd.edu Mask (Reticle) Manufacturing MEBES format and machine, or others Place a glass plate covered with chrome covered with resist in a high-vacuum column Use an electron beam spot size smaller than the finest resolution of the design Scan the surface of the mask with the e- beam in a raster-scan order. Modulate the beam to transfer the pattern to the chrome Develop the resist, and the chrome, and then remove the resist Check and correct the chrome pattern.... All modern processes use masks (reticles) that are 5-10x larger than the desired size. The mask aligners then project the image and reduce it in the projection. While this means that exposing a wafer takes multiple prints, it is needed to reach the resolutions needed for current technologies. Courtesy K. Yang, UCLA
ECE 260B – CSE 241A Manufacturing 9http://vlsicad.ucsd.edu “Yield” in the Semiconductor Industry Yield : something yielded: PRODUCT; especially: the amount or quantity produced or returned. Assessment of the quality of the design. Design for manufacturability (DFM). Manufacturability : measure of the number of defect-free chips that can be produced from a single wafer . Manufacturability M = N chip * Y C chip = C wf /(N chip * Y)
ECE 260B – CSE 241A Manufacturing 10http://vlsicad.ucsd.edu Why DFM? DFM: optimization of designs for maximum yield in the presence of contamination. (a). High wafer yield through contamination control has become difficult and hard to achieve. (b). Increase in fabless design houses, which have little control over the manufacturing process; can control costs only by optimizing designs for higher yield . Prediction of the IC area and yield is, therefore, critical to any sound IC design methodology.
ECE 260B – CSE 241A Manufacturing 11http://vlsicad.ucsd.edu Yield Loss in ICs Yield loss occurs when there is an unacceptable mismatch between the expected and actual parameters of an IC. Yield loss in ICs are classified into two types: (a).Functional yield loss (Y fnc ) due to spot defects (shorts & opens). (b).Parametric yield loss (Y par ) due to global process disturbances. Defects: circular disks of extra/missing material in any layer of the IC . Total Yield = Y fnc * Y par
ECE 260B – CSE 241A Manufacturing 12http://vlsicad.ucsd.edu “Critical Area” in ICs The susceptibility of an IC layer to a defect is captured by the “critical area” function. The critical area for a defect of radius r d is defined as that area on a die where if the center of a circular defect falls, a fault occurs in the circuit .
ECE 260B – CSE 241A Manufacturing 13http://vlsicad.ucsd.edu Interconnect Yield Model The yield loss primarily takes place in the metals: (a). The use of the metal layer is more extensive than that of any other layer in the IC. (b). The defect count is more in the metal layer. Poisson’s yield model: Y = exp(-A*D); A = die area; D = defect density. The interconnect yield Y of the chip  : ACr= critical area; r 0 = defect radius; r 1 = half (the min. Spacing between metals); K and p are model parameters.
ECE 260B – CSE 241A Manufacturing 14http://vlsicad.ucsd.edu Extraction of Critical Area for Shorts Step 1: Expand each geometry shape by radius R. Step 2: Find the intersection area of such expanded geometry. Step 3: Find the union of all intersection area. Step 4: Repeat steps 1, 2, and 3 for a range of defect sizes .
ECE 260B – CSE 241A Manufacturing 15http://vlsicad.ucsd.edu Extraction of Critical Area for Opens Step 1: Shrink both the edges of the conducting path by radius R; extend the left and right edges of the shrunk conducting path by radius R. Step 2: Shrink all edges of the rectangular contact by radius R. Step 3: Find the union of the shrunk area. Step 4: Repeat steps 1, 2, and 3 for a range of defect sizes .
ECE 260B – CSE 241A Manufacturing 16http://vlsicad.ucsd.edu Critical Area in the IC Layout
ECE 260B – CSE 241A Manufacturing 17http://vlsicad.ucsd.edu Yield Dependence on the Critical Area of an IC
ECE 260B – CSE 241A Manufacturing 18http://vlsicad.ucsd.edu Yield Enhancement by Layout Optimization Design of appropriate cells, that are small in size. Choosing smart place and route strategies/optimization of wire spacing. (a). Additional Interconnect layers. (b). Reducing Cell Utilization. (c). Relaxing metal design rules .
ECE 260B – CSE 241A Manufacturing 20http://vlsicad.ucsd.edu Optical Proximity Correction (OPC) Layout modifications improve process control l improve yield (process latitude) l improve device performance Complicates mask manufacturing and increases cost Post-design verification is needed With OPC No OPC Original Layout (Attenuated PSM) OPC Corrections
ECE 260B – CSE 241A Manufacturing 21http://vlsicad.ucsd.edu OPC Mechanisms Serifs: corner rounding Hammerheads: line-end shortening Gate assists (subresolution scattering bars): CD control Gate biasing: CD control Affects custom, hierarchical and reuse-based layout methodologies
ECE 260B – CSE 241A Manufacturing 22http://vlsicad.ucsd.edu Rule-Based OPC vs. Model-Based OPC Rule-Based OPC l Apply corrections based on a set of predetermined rules l Fast design time, lower mask complexity l Suitable for less aggressive designs Model-Based OPC l Use process simulation to determine corrections on-line l Longer design time, increased mask complexity l Suitable for aggressive designs
ECE 260B – CSE 241A Manufacturing 23http://vlsicad.ucsd.edu OPC Issues Pass functional intent down to OPC insertion l OPC insertion is for predictable circuit performance, function l Make only the corrections that win $$$ by reducing performance variation cost-driven reticle enhancement technology (RET) Pass limits of manufacturing up to layout l don’t make corrections that can’t be manufactured or verified l Mask Error Enhancement Factor Layout needs models of OPC insertion process l geometry effects on cost of required OPC to yield function l costs of breaking hierarchy (beyond known verification, characterization costs)
ECE 260B – CSE 241A Manufacturing 25http://vlsicad.ucsd.edu Context dependence: Same pattern, different fracture P. Buck, Dupont Photomasks – ISMT Mask-EDA Workshop July 2001 $1M NRE: Mask Write and Inspection Times
ECE 260B – CSE 241A Manufacturing 26http://vlsicad.ucsd.edu $1M NRE: Mask Write and Inspection Times Too many data formats l Most tools have unique data format l Raster to variable shaped-beam conversion is inefficient l Real-time manufacturing tool switch, multiple qualified tools duplicate fractures to avoid delays if tool switch required Data volume l OPC increases figure count acceleration l MEBES format is flat l ALTA machines (mask writers) slow down with > 1GB data l Data volume strains distributed manufacturing resources Refracturing mask data l 90% of mask data files manipulated or refractured: process bias sizing (iso-dense, loading effects, linearity, …), mask write optimization, multiple tool formats, …
ECE 260B – CSE 241A Manufacturing 27http://vlsicad.ucsd.edu MEBES Data Volume (GB) Year P. Buck, Dupont Photomasks – ISMT Mask-EDA Workshop July 2001 ITRS Maximum Single Layer File Size
ECE 260B – CSE 241A Manufacturing 28http://vlsicad.ucsd.edu ABF Data Volume (MB) Write Time (Reformat + Print) (Hrs) P. Buck, Dupont Photomasks – ISMT Mask-EDA Workshop July 2001 Mask Write Time vs. Data Volume
ECE 260B – CSE 241A Manufacturing 29http://vlsicad.ucsd.edu Fracturing Problem Mask Data Process Flow Layout Extraction RET Circuit Design Tape Out Job Decomposition Mask Data Preparation Mask Making Writing Inspection Metrology Tonality PEC Fracturing Job Finishing Fracturing
ECE 260B – CSE 241A Manufacturing 30http://vlsicad.ucsd.edu Challenges in Fracturing A shot whose minimum width < is called a sliver < sliver slant # shots increase mask writing time increasecost increase each shot should be an axis-parallel trapezoid the side size of each shot < M slant edges should not be partitioned # slivers increase mask error enhancement factor (MEEF) increase larger CD variation and error yield decrease
ECE 260B – CSE 241A Manufacturing 31http://vlsicad.ucsd.edu Fracturing Problem a list of polygons P with axis parallel and slant edges Max shot size M Slivering size Partition P into non-overlapping trapezoidal shots Number of shots and number of slivers Given: Minimizing: Normal fracturing Reverse tone fracturing
ECE 260B – CSE 241A Manufacturing 32http://vlsicad.ucsd.edu A “Ray Selection” Problem Two candidates to kill one concave point For each concave point (include inner point), choose one out of two candidate rays to minimize # slivers They are called as “conflict pair”
ECE 260B – CSE 241A Manufacturing 33http://vlsicad.ucsd.edu Applicability of OPC and PSM
ECE 260B – CSE 241A Manufacturing 34http://vlsicad.ucsd.edu Mask NRE Cost (SEMATECH, 1999) “$1M mask set” at 100nm, but average only 500 wafers per set
ECE 260B – CSE 241A Manufacturing 35http://vlsicad.ucsd.edu The light interacting with the mask is a wave Any wave has certain fundamental properties l Wavelength ( ) l Direction l Amplitude l Phase RET is wavefront engineering to enhance lithography by controlling these properties RET Basics Amplitude Direction Phase Courtesy F. Schellenberg, Mentor Graphics Corp.
ECE 260B – CSE 241A Manufacturing 36http://vlsicad.ucsd.edu Phase: PSM Phase Shifting Masks (PSM) etch topography into mask l Creates interference fringes on the wafer Interference effects boost contrast Phase Masks can make extremely small gates conventional mask glass Chrome Electric field at mask Intensity at wafer phase shifting mask Phase shifter
ECE 260B – CSE 241A Manufacturing 37http://vlsicad.ucsd.edu Forms of Bright-Field Alternating PSM Single exposure l phase transitions required, e.g., 0-60-120-180 or 90-0-270 to avoid printing phase edges l throughput unaffected l limited improvement in process latitude l mask manufacturing difficult, mask cost very high Double exposure l PSM with 0 and 180 degree phase shifters l define only critical features ("locally bright-field"), rest of mask is chrome l second exposure with clear-field binary mask protects critical features, defines non-critical features as well l better process latitude l decrease in throughput (double exposure) 90°270° 180° 60° 120° 0°
ECE 260B – CSE 241A Manufacturing 40http://vlsicad.ucsd.edu The Phase Assignment Problem Assign 0, 180 phase regions such that critical features with width < B are induced by adjacent phase regions with opposite phases 0180
"name": "ECE 260B – CSE 241A Manufacturing 40http://vlsicad.ucsd.edu The Phase Assignment Problem Assign 0, 180 phase regions such that critical features with width < B are induced by adjacent phase regions with opposite phases 0180
ECE 260B – CSE 241A Manufacturing 41http://vlsicad.ucsd.edu Phase Assignment for Bright-Field PSM PROPER Phase Assignment: l Opposite phases for opposite shifters l Same phase for overlapping shifters Overlapping shifters
ECE 260B – CSE 241A Manufacturing 42http://vlsicad.ucsd.edu Key: Global 2-Colorability ? 180 0 0 Odd cycle of “phase implications” layout cannot be manufactured l layout verification becomes a global, not local, issue
ECE 260B – CSE 241A Manufacturing 43http://vlsicad.ucsd.edu Phase Conflict and the Conflict Graph Self-consistent phase assignment is not possible if there is an odd cycle in the conflict graph Phase-assignable = conflict graph is bipartite = no odd cycles l this is a global issue! l features on one side of chip can affect features on the other side Breaking odd cycles: must change the layout! l change feature dimensions, and/or change spacings l Many degrees of freedom, e.g., layer reassignment for interconnects
ECE 260B – CSE 241A Manufacturing 44http://vlsicad.ucsd.edu Conflict Graph Bright Field: build graph over shifter regions l shifters for features whose width is < B l two edge types l adjacency edge between overlapping phase regions : endpoints must have same phase l conflict edge between shifters on opposite side of critical feature: endpoints must have opposite phase
ECE 260B – CSE 241A Manufacturing 51http://vlsicad.ucsd.edu F4 F2 F1 S1 S2 S3S4 S7S8 Phase Conflict feature widening to turn conflict into non-conflict Conflict Resolution: Widening F3
ECE 260B – CSE 241A Manufacturing 52http://vlsicad.ucsd.edu Minimum Perturbation Problem Layout modifications l feature shifting l feature widening area increase, slowing down manual fixing, design cost increase Minimum Perturbation Problem: Find min # of layout modifications leading to proper phase assignment. [Kahng et al. ASPDAC 2001]
ECE 260B – CSE 241A Manufacturing 53http://vlsicad.ucsd.edu PSM = Whose Problem? Must partition responsibility for phase-assignability into at least three domains Good layout practices l No T’s, no doglegs, even-length fingers on transistors, … l Open problem: What “design rules” guarantee phase-assignability without too much loss of density? Automatic phase conflict resolution Reuse of pre-existing layout l E.g., the entire standard-cell methodology is based on the assumption of “free composability” of cells within rows (as long as the cells don’t overlap) l Open problem: How to phase-assign layouts, such that no odd cycles of conflict occur when the layouts are composed
ECE 260B – CSE 241A Manufacturing 54http://vlsicad.ucsd.edu Conflict Graph for Cell-Based Layouts Coarse view: at level of connected components of conflict graphs within each cell master -each of these components is independently phase-assignable -can be treated as a single “vertex” in coarse-grain conflict graph edge in coarse-grain conflict graph cell master Acell master B connected component
ECE 260B – CSE 241A Manufacturing 55http://vlsicad.ucsd.edu “Compaction-Based” PSM Layout Flow Analyze input layout Find min-cost set of perturbations needed to eliminate all “odd cycles” Induce shape, spacing constraints for new output layout “Compact” to get phase-assignable layout Goal: Minimize the set of new constraints, i.e., break all odd cycles in conflict graph by deleting a minimum number of edges
ECE 260B – CSE 241A Manufacturing 56http://vlsicad.ucsd.edu Conflict Edge Weight Which conflict edges are cheapest to break? Critical paths (e.g., in compactor) in x- and y- directions define layout area Conflict edges not on critical path: break for free l Criticality: with respect to, e.g., area or timing critical path
ECE 260B – CSE 241A Manufacturing 57http://vlsicad.ucsd.edu Density Control for CMP
ECE 260B – CSE 241A Manufacturing 58http://vlsicad.ucsd.edu Damascene and Dual-Damascene Process Damascene process named after the ancient Middle Eastern technique for inlaying metal in ceramic or wood for decoration Single Damascene Dual Damascene ILD Deposition Oxide Trench Etch Metal Fill Metal CMP Oxide Trench / Via Etch Metal Fill Metal CMP
ECE 260B – CSE 241A Manufacturing 59http://vlsicad.ucsd.edu Layout Density Control Flow Density Analysis find total feature area in each window find maximum/minimum total feature area over all w w windows Fill synthesis compute amounts, locations of dummy fill generate fill geometries find slack (available area for filling) in each window
ECE 260B – CSE 241A Manufacturing 60http://vlsicad.ucsd.edu Fixed r-Dissection Regime Feature area density bounds enforced only for fixed set of w w windows Layout partitioned by r 2 distinct fixed dissections Each w w window is partitioned in r 2 tiles How different is this from the regime of “continuous” window locations? tile overlapping windows fixed r-dissection with r = 4
ECE 260B – CSE 241A Manufacturing 61http://vlsicad.ucsd.edu Filling Problem
ECE 260B – CSE 241A Manufacturing 62http://vlsicad.ucsd.edu Filling Problem in Fixed-Dissection Regime Given design rule-correct layout of k disjoint rectilinear features in an n n layout region Find design rule-correct filled layout, such that l no fill geometry is added within distance B of any layout feature l no fill is added into any window that has density U l minimum window density in the filled layout is maximized (or has density lower bound L) Given l fixed r-dissection of layout l feature area[T] in each tile T l slack[T] = area available for filling in T l maximum window density U Find l total fill area p[T] to add in each T s.t. any w w window W has density U l min W T W (area[T] + p[T]) is maximized
ECE 260B – CSE 241A Manufacturing 63http://vlsicad.ucsd.edu Synthesis of Filling Patterns Given area of filling pattern p[i,j], insert filling pattern into tile T[i,j] uniformly over available area Desirable properties of filling pattern l uniform coupling to long conductors l either grounded or floating
ECE 260B – CSE 241A Manufacturing 64http://vlsicad.ucsd.edu Basket-Weave Fill Pattern Each vertical/horizontal crossover line has same overlap capacitance to fill
ECE 260B – CSE 241A Manufacturing 65http://vlsicad.ucsd.edu Grounded Fill Pattern Fill with horizontal stripes, then span with vertical lines
ECE 260B – CSE 241A Manufacturing 66http://vlsicad.ucsd.edu Flow Implications Accurate estimation of filling is needed in PD, PV tools (else broken performance analysis flow) Filling geometries affect capacitance extraction by > 50% Multilayer problem (coupling to critical nets, contacting restrictions, active layers, other interlayer dependencies)
ECE 260B – CSE 241A Manufacturing 67http://vlsicad.ucsd.edu Issues With Current Tools Only the average overall feature density is constrained, while local variation in feature density is ignored Density analysis does not find true extremal window densities - instead, it finds extremal window densities only over fixed set of window positions Fill insertion into layout does not minimize the maximum variation in window density In part, due to physical verification tool heritage l Boolean operations l Never empowered to change the layout
ECE 260B – CSE 241A Manufacturing 68http://vlsicad.ucsd.edu Len Aberration Example: Field-dependent aberrations cause placement errors and distortions ( location-specific cell variants?) Center: Minimal Aberrations Edge: High Aberrations Towards Lens Wafer Plane Lens R. Pack, Cadence