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**Lecture #9 EGR 277 – Digital Logic**

Reading Assignment: Chapter 4 in Digital Design, 3rd Edition by Mano Magnitude Comparators A magnitude comparator is a device that can be used to compare two binary inputs. The output will indicate if the inputs are equal or else which input is the largest. Comparing for equality Exclusive-NOR (equivalence) gates can be used to compare binary values. 1-bit comparison for equality: 4-bit comparison for equality: Two 4-bit words A = A3A2A1A0 and B = B3B2B1B0 are equal if A3 = B3 , A2 = B2 , etc.

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**Lecture #9 EGR 277 – Digital Logic**

Comparing to determine if A > B, A < B, or A = B A typical block diagram for a 4-bit comparator is shown. Algorithm for A > B: . if A3 = 1 and B3 = 0, (A3' B3 ) then A > B . if A3 = B3 (i.e., x3 - see previous page) and A2 = 1 and B2 = 0, (x3A2' B2 ) then A > B . etc. . Develop expressions for A>B and A<B

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**Lecture #9 EGR 277 – Digital Logic**

Diagram for 4-bit comparator based on algorithm’s developed on the last page:

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**Lecture #9 EGR 277 – Digital Logic**

Commercially available 4-bit comparator: Discuss what values to use for A>Bin, A=Bin, and A<Bin Show how two 7485’s can be used to form an 8-bit comparator

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**Lecture #9 EGR 277 – Digital Logic**

Encoder An encoder is essentially the opposite of a decoder. An N-bit encoder has 2N inputs lines, one of which is active, and N output lines that carry the binary code corresponding to the active input. The 8 x 3 encoder shown below might also be called an octal-to-binary encoder. Example: Show an encoder with sample inputs and outputs.

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**Lecture #9 EGR 277 – Digital Logic**

Note that encoders and decoders perform the opposite functions. Example: Show an 8x3 encoder followed by a 3x8 decoder with some sample inputs and outputs. Example: Show a 3x8 decoder followed by an 8x3 encoder with some sample inputs and outputs.

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**Lecture #9 EGR 277 – Digital Logic**

Basic Encoder Design An 8x3 encoder has 3 outputs whose functions can be determined using the Karnaugh maps below. Sketch the circuit. D0 D1 D3 D2 D4 D5 D7 D6 00 01 11 10 1 D0 D1 D3 D2 D4 D5 D7 D6 00 01 11 10 1 D0 D1 D3 D2 D4 D5 D7 D6 00 01 11 10 1 Valid Output? One problem with the encoder design above is that there is no way to indicate that an invalid input occurred. This problem can be resolved by using an additional output called a valid line, V. D0 D1 D2 D3 D4 D5 D6 D7 Output Code V = 1 for a valid code (0 if invalid) 8 x 3 Encoder 2 1 x y z V

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**Lecture #9 EGR 277 – Digital Logic**

Encoders - Application Decoders can be used to reduce the number of wires needed to control multiple outputs. Encoders can be used to reduce the number of wires needed to read multiple inputs. Example: Suppose that a computer was used to read the status of 256 sensors in a special application where only one sensor would ever be HIGH at a given time. One option would be to find a 256-pin connector to work with the computer (good luck). A better option would be to use an 256x8 encoder and use an 8-bit connector on the computer. The computer could then simply read the code to determine which sensor was activated.

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**Lecture #9 EGR 277 – Digital Logic**

Example: IEEE sponsors competitions for students in electrical and computer engineering. In 1998 the IEEE SouthEastCon was held at Virginia Tech and Computer Engineering students were given the challenge of designing a piece of Windows-based software to control an HO-scale train. A track was set up with 32 sensors. A sensor would read HIGH when the train was over it and LOW otherwise. A 32 x 5 encoder was used to encode the sensor information. The train, track, sensors, and encoder were provided and the distance between the sensors was specified. Student teams had to write software to: 1) stop and start the train at any sensor location 2) execute a planned train route 3) display the speed of the train etc. 32 x 8 Encoder .

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**. Lecture #9 EGR 277 – Digital Logic Priority Encoder**

A priority encoder is an encoder where: more than one input may be activated each input is assigned a priority the output code corresponds to the highest priority input that has been activated. D7 D6 D5 D4 D3 D2 D1 D0 Output Code V = 1 for a valid code (0 if invalid) 8 x 3 Priority Encoder 2 1 x y z V Highest priority Lowest priority . Example: Show a priority encoder with several activated inputs

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**Lecture #9 EGR 277 – Digital Logic**

Example: Show the truth table for an 8x3 priority encoder with an output line V with active-HIGH inputs and outputs. Repeat if all outputs are active-LOW.

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**Lecture #9 EGR 277 – Digital Logic**

Example: A computer uses “interrupts” to allow peripheral devices, such as modems, printers, disk drives, scanners, cameras, etc., to request attention from the computer. But the computer can only do one task at a time, so they are assigned priorities such as in the table shown below. Discuss using a priority encoder as an “interrupt handler”.

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08/07/041 CSE-221 Digital Logic Design (DLD) Lecture-8:

08/07/041 CSE-221 Digital Logic Design (DLD) Lecture-8:

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