Presentation on theme: "Half Adder Sec. 3.10 Sec. 4.5, 4.12. Schedule 11/13MondayCourse intro, diagnostic test 21/15Wednesday Fundamentals of digital logic design (1) (signed."— Presentation transcript:
Schedule 11/13MondayCourse intro, diagnostic test 21/15Wednesday Fundamentals of digital logic design (1) (signed numbers) L1/16ThursdayRules, cleaning procedure, linux &Cadence intro. N/A1/20MondayMLK Day (Campus Closed) 31/22Wednesday Fundamentals of digital logic design (2) (Context: Verilog) L1/23ThursdayNAND based NOR gates (Verilog) 41/27MondayNAND based NOT and NOR (Breadboard) 51/29WednesdayBinary addition: half adder L1/30ThursdayBinary: half adder 62/3MondayBinary addition: full adder 72/5WednesdayBinary addition: four-bit adder/subtractor L2/6ThursdayClass Canceled 82/10MondayClass Canceled Test #1: Beginning of March
Outline Transition from Verilog to Digital Logic Observations Verilog Lesson Application: Half Adder
Observations Lab submissions are due at the beginning of the next lab, i.e. the following Thursday. Path to the files/`timescale Need One bit file per input Power Supply: Tie the common reference ground.
`timescale Comment `out timescale Each time interval is one second. Need to update the path! $readmemb(“./bit_str_a_0.txt”,t_A); Default directory: verilogSandBox
Need One bit file Per Input C D E F G1 G2 G3G4 Remember to pull the numbers out of the registry. Need one bit file per input!
Lessons on Verilog Verilog – Running Command Line Verilog $monitor– output the data to the monitor $fmonitor—save data to an output file – Module/module test bench template – assign – Bitwise logic operator
Two Ways of Running Verilog Running Verilog Using the GUI Writing Output to a file Advantage: Avoid the GUI Disadvantage: hard to visualize an input pattern
Running Verilog at Command Prompt $monitor $fmonitor
Writing Output to a file 1. Declare a file pointer 2. Open a file, specify the file name 3. Use $fmonitor to write to a file 4. Close the file after 1000 time intervals 5. Finish the simulation
Module Template module module_name (,, ); endmodule Input, output wires reg Program Body
Module Test BenchTemplate //`timescale 1 ms /1 us module module_tb_name (,, ); endmodule Input, output wires reg Define the test bench Call on the module
Your First Verilog Program module fig3p37 (A,B,C,D,E); output D,E; input A,B,C; wire w1; and G1(w1,A,B); not G2(E,C); or G3(D,w1,E); endmodule And, not or are primitive gates. The output of a primitive gate is always listed first. The inputs can be listed in any order. G1 is an instance of the and gate.
Rewrite the Program Using assign Use & for AND operation Use tilda (~) for the INVERT operation Use | for the OR operation You can think of a wire as a wire in a circuit where actual voltages Could be measured.
Keyword: assign assign : the assignment is said to be sensitive to the variables in the RHS expression because anytime a variable in the RHS changes during the simulation, the RHS expression is reevaluated and the result is used to update the LHS. – RHS: R ight H and S ide of = – LHS: L eft H and S ide of = wire elements are the only legal type on the left hand side of an assign statement. (More about this next time)
Bitwise Logic Operation Bitwise means 1 bit at a time Bitwise logic operator Verilog ANDa&b ORa|b XORa^b INVERT~a NAND~(a&b) NOR~(a|b) XNOR!(a^b)