Things to Sort Through before writing the module four_bit_adder.v – What should be declared as inputs? – What should be declared as outputs? – How do I connect the ports of four_bit_add.v module to ports of full_adder.v module? – What should be declared as wires – What verilog modules should I include? – How should the instance be invoked?
Things to Sort Through Before Writing the Module four_bit_adder_tb.v – What test bench should I use as a template? – What should be the output? – What wires should I have? – What should I replace t_X,t_Y, t_Z with? – How should the four_bit_adder.v be invoked? – How should the output be printed?
What Will Be provided? Bit files (9 files in all, downloadable from the course website) half_adder.v What you need to implement: – full_adder.v – full_adder_tb.v – four_bit_adder.v – four_bit_adder_tb.v Due date: Next Wed (2/12) in Class.