2 Schedule 10 2/17 Monday Decoder 11 2/19 Wednesday Encoder (hw3 is assigned)L2/20ThursdayDecoder Experiment122/24MUX/Three state (data flow versus behavioral)132/26Catch-up (hw3 is due)2/27Random number generator143/3Test 1
4 Feedback on the labs Tutorial Finish the labs before you leave. emacs/vi tutorial at the course webpage.Verilog tutorialAlways start from the textbook (There is usually a section on Verilog at the end of each chapter)Supplement the textbook with the tutorial from ASIC.Use the existing sample code as a starting point.Finish the labs before you leave.
25 Basic SRAM and VTC A wordline is used to select the cell Bitlines are used to perform read and write operations on the cell
26 Cross Coupled Configuration The cell can only flip its internal state when one of its internal cross VS.During a read op, we must not disturb its current state.During a write op, we must force the internal voltage to swing past VS to change a state.