Presentation on theme: "Verilog Section 3.10 Section 4.5. Keywords Keywords are predefined lowercase identifiers that define the language constructs – Key example of keywords:"— Presentation transcript:
Keywords Keywords are predefined lowercase identifiers that define the language constructs – Key example of keywords: module, endmodule, input, output, and wire.
assign The assignment is said to be sensitive to the variables in the RHS expression because anytime a variable in the RHS changes during the simulation, the RHS expression is reevaluated and the result is used to update the LHS.
Semicolon Each statement must end with a semicolon (;)
Bitwise Logic Operation Bitwise means 1 bit at a time Bitwise logic operatorVerilog ANDa&b ORa|b XORa^b INVERT~a NAND~(a&b) NOR~(a|b) XNOR!(a^b)
wire You can think of a wire as a wire in a circuit where actual voltages Could be measured.
Wire example Use & for AND operation Use tilda (~) for the INVERT operation Use | for the OR operation
Using Verilog Primitives Verilog also has keywords such as and or and not. The output of a primitive must be listed first.
Gate Delays In Verilog, the propagation delay of a gate is specified in terms of time units and is specified by the symbol #. `timescale 1ns/100ps – The first number specifies the unit of measurement for time delays. – The second number specifies the precisions for which the delays are rounded off.
Schematic of a Full Adder Half-adder(not including the bubble) Half-adder
Build a Verilog Representation of a Full Adder Circuit Build a half adder circuit Build a test bench for the adder circuit Assemble a full adder circuit Build a test bench circuit to test the full –adder Write the code to implement the adder circuit on FPGA
Build a Test Bench in Verilog Ideas: (page 112 of the textbook) 1.reg 2.Initial statement 3.Assign value to a single bit 4.$finish 1’b0=one binary digit with a value of 0 1’b1=one binary digit with a value of 1
Initial, $finish inital: keyword used with a set of statements that begin executing when simulation is initialized. $finish: specifies the termination of simulation.
Block statement A block statement consists of several statements that are executed in sequence from top to bottom.