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Verilog Section 3.10 Section 4.5

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Keywords Keywords are predefined lowercase identifiers that define the language constructs – Key example of keywords: module, endmodule, input, output, and wire.

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assign The assignment is said to be sensitive to the variables in the RHS expression because anytime a variable in the RHS changes during the simulation, the RHS expression is reevaluated and the result is used to update the LHS.

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Semicolon Each statement must end with a semicolon (;)

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Bitwise Logic Operation Bitwise means 1 bit at a time Bitwise logic operatorVerilog ANDa&b ORa|b XORa^b INVERT~a NAND~(a&b) NOR~(a|b) XNOR!(a^b)

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wire You can think of a wire as a wire in a circuit where actual voltages Could be measured.

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Wire example Use & for AND operation Use tilda (~) for the INVERT operation Use | for the OR operation

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Waveform

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Using Verilog Primitives Verilog also has keywords such as and or and not. The output of a primitive must be listed first.

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Gate Delays In Verilog, the propagation delay of a gate is specified in terms of time units and is specified by the symbol #. `timescale 1ns/100ps – The first number specifies the unit of measurement for time delays. – The second number specifies the precisions for which the delays are rounded off.

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Gate Delay E is not defined until after 1 ns.

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Gate Delay E is not defined until 1 ns. W is not defined until 2 ns. This means that D is not defined until 3 ns.

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Binary Addition Example

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Derivation of ∑ (ES112 Slides) BA∑ 000 101 011 110

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Derivation of Carry Out (ES112 Slides) Question: What primitive best implements C o ? Inputs: A, B Outputs: C o =A∙B BACoCo 000 100 010 111

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Implementation of a Half-Adder

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Limitation of a Half Adder A half-adder does not account for carry-in.

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Truth Table for a Full Adder carry-in

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Karnaugh Map For the Sum Bit (ES112 Review)

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Karnaugh Map For the Carry-Out Bit (ES112 Review)

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Implementation of a Full Adder (carry-in)

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Schematic of a Full Adder Half-adder(not including the bubble) Half-adder

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Build a Verilog Representation of a Full Adder Circuit Build a half adder circuit Build a test bench for the adder circuit Assemble a full adder circuit Build a test bench circuit to test the full –adder Write the code to implement the adder circuit on FPGA

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Build a Half-Adder Circuit (Figure 4.5)

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Build a Test Bench in Verilog Ideas: (page 112 of the textbook) 1.reg 2.Initial statement 3.Assign value to a single bit 4.$finish 1’b0=one binary digit with a value of 0 1’b1=one binary digit with a value of 1

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Initial, $finish inital: keyword used with a set of statements that begin executing when simulation is initialized. $finish: specifies the termination of simulation.

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Block statement A block statement consists of several statements that are executed in sequence from top to bottom.

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Build a Full-Adder Circuit w1 w2w3 M1M2

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Full-Adder Top Level Circuit

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Build a FPGA Top Level Circuit (x) (y) (z)(s) (c) See gates2.pdf (available from the course website) for reference

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Introduction to Verilog Section 3.10. Outline Set Up the Environment Your First Verilog File Set Up the Test Bench Running the Simulation.

Introduction to Verilog Section 3.10. Outline Set Up the Environment Your First Verilog File Set Up the Test Bench Running the Simulation.

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