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Multiplexers Section 3-7 Mano & Kime

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Multiplexers & Demultiplexers Multiplexers (Selectors) Lab 1 – Behavioral VHDL -- Multiplexers MUX as a Universal Element

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4– to– 1- Line Multiplexer

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4–to–1-Line Multiplexer with Transmission Gates

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Quadruple 2–to–1-Line Multiplexer

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Typical uses

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Multiplexers Multiplexers (Selectors) Lab 1 – Behavioral VHDL -- Multiplexers MUX as a Universal Element

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Combinational Circuit Example n-line 2-to-1 Multiplexer n-line 2 x 1 MUX a(n-1:0) b(n-1:0) y(n-1:0) sel sel y 0 a 1 b

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library IEEE; use IEEE.std_logic_1164.all; entity mux2g is generic (width:positive); port ( a: in STD_LOGIC_VECTOR(width-1 downto 0); b: in STD_LOGIC_VECTOR(width-1 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(width-1 downto 0) ); end mux2g; An n-line 2 x 1 MUX a(n-1:0) b(n-1:0) y(n-1:0) sel n-line 2 x 1 MUX

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library IEEE; use IEEE.std_logic_1164.all; entity mux2g is generic (width:positive); port ( a: in STD_LOGIC_VECTOR(width-1 downto 0); b: in STD_LOGIC_VECTOR(width-1 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(width-1 downto 0) ); end mux2g; Entity Each entity must begin with these library and use statements port statement defines inputs and outputs generic statement defines width of bus

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library IEEE; use IEEE.std_logic_1164.all; entity mux2g is generic (width:positive); port ( a: in STD_LOGIC_VECTOR(width-1 downto 0); b: in STD_LOGIC_VECTOR(width-1 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(width-1 downto 0) ); end mux2g; Entity Mode: in or out Data type: STD_LOGIC, STD_LOGIC_VECTOR(width-1 downto 0);

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Standard Logic type std_ulogic is (‘U’, -- Uninitialized ‘X’ -- Forcing unknown ‘0’ -- Forcing zero ‘1’ -- Forcing one ‘Z’ -- High impedance ‘W’ -- Weak unknown ‘L’ -- Weak zero ‘H’ -- Weak one ‘-’); -- Don’t care library IEEE; use IEEE.std_logic_1164.all;

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Standard Logic Type std_ulogic is unresolved. Resolved signals provide a mechanism for handling the problem of multiple output signals connected to one signal. subtype std_logic is resolved std_ulogic;

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architecture mux2g_arch of mux2g is begin mux2_1: process(a, b, sel) begin if sel = '0' then y <= a; else y <= b; end if; end process mux2_1; end mux2g_arch; Architecture a(n-1:0) b(n-1:0) y(n-1:0) sel n-line 2 x 1 MUX Note: <= is signal assignment

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architecture mux2g_arch of mux2g is begin mux2_1: process(a, b, sel) begin if sel = '0' then y <= a; else y <= b; end if; end process mux2_1; end mux2g_arch; Architecture entity name process sensitivity list Sequential statements (if…then…else) must be in a process Note begin…end in process Note begin…end in architecture

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Digilab2 – DIO1 Boards Spartan II FPGA 8 LEDs LD 8 Switches SW 4 Pushbuttons BTN Four 7-segment displays Pushbutton bn 74HC373 latch ldg <= ‘1’

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Top-level Design – Lab 1

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library IEEE; use IEEE.std_logic_1164.all; entity lab1 is port ( SW: in STD_LOGIC_VECTOR (1 to 8); BTN4: in STD_LOGIC; ldg: out STD_LOGIC; LD: out STD_LOGIC_VECTOR (1 to 4) ); end lab1;

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architecture lab1_arch of lab1 is component mux2g generic(width:positive); port ( a: in STD_LOGIC_VECTOR (width-1 downto 0); b: in STD_LOGIC_VECTOR (width-1 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR (width-1 downto 0) ); end component; constant bus_width: positive := 4; begin ldg <= '1'; -- enable 74HC373 latch SWmux: mux2g generic map(width => bus_width) port map (a => SW(1 to 4), b => SW(5 to 8), sel => BTN4, y => LD); end lab1_arch;

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An n-line 4 x 1 multiplexer a(n-1:0) b(n-1 :0) y(n-1 :0) sel(1:0) 8-line 4 x 1 MUX c(n-1 :0) d(n-1 :0) Sely “00”a “01”b “10”c “11”d

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An 8-line 4 x 1 multiplexer library IEEE; use IEEE.std_logic_1164.all; entity mux4g is generic(width:positive); port ( a: in STD_LOGIC_VECTOR (width-1 downto 0); b: in STD_LOGIC_VECTOR (width-1 downto 0); c: in STD_LOGIC_VECTOR (width-1 downto 0); d: in STD_LOGIC_VECTOR (width-1 downto 0); sel: in STD_LOGIC_VECTOR (1 downto 0); y: out STD_LOGIC_VECTOR (width-1 downto 0) ); end mux4g;

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Example of case statement architecture mux4g_arch of mux4g is begin process (sel, a, b, c, d) begin case sel is when "00" => y <= a; when "01" => y <= b; when "10" => y <= c; when others => y <= d; end case; end process; end mux4g_arch; Must include ALL posibilities in case statement Note implies operator => Sely “00”a “01”b “10”c “11”d

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VHDL Architecture Structure architecture name_arch of name is begin end name_arch; Signal assignments Concurrent statements Process 1 Process 2 Concurrent statements Processes contain sequential statements, but execute concurrently within the architecture body

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VHDL Process P1: process (

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Multiplexers Multiplexers (Selectors) Lab 1 – Behavioral VHDL -- Multiplexers MUX as a Universal Element

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Multiplexer as universal combinational module connect input variables x to select inputs of multiplexer s set data inputs to multiplexer equal to values of function for corresponding assignment of select variables using a variable at data inputs reduces size of the multiplexer

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Implementing a Boolean Function with a Multiplexer

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Implementing a Four- Input Function with a Multiplexer

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Networks with 2-input multiplexers

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Implementation of SFs with network of MUXes

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Design of networks with MUXes

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Example

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Ordering of variables in subtrees affects the number of MUXes

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Example of Shannon’s Decomposition F = x 3 (x 1 + x 2 x 0 ) Implemented using a multiplexer network

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F = x 3 (x 1 + x 2 x 0 ) Start with any variable - x 0 for example x 0 = 0 x 0 = 1 F = x 3 x 1 F = x 3 (x 1 + x 2 )

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F = x 3 (x 1 + x 2 x 0 ) Then x ! for example x 0 = 0 x 0 = 1 F = x 3 x 1 F = x 3 (x 1 + x 2 ) x 1 = 0 x 1 = 1 F = 0 F = x 3 x 1 = 0 x 1 = 1 F = x 3 x 2 F = x 3

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F = x 3 (x 1 + x 2 x 0 ) Then x 2 for example x 0 = 0 x 0 = 1 F = x 3 x 1 F = x 3 (x 1 + x 2 ) x 1 = 0 x 1 = 1 F = 0 F = x 3 x 1 = 0 x 1 = 1 F = x 3 x 2 F = x 3 x 2 = 0 x 2 = 1 F = 0 F = x 3

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F = x 3 (x 1 + x 2 x 0 ) x 0 = 0 x 0 = 1 F = x 3 x 1 F = x 3 (x 1 + x 2 ) x 1 = 0 x 1 = 1 F = 0 F = x 3 x 1 = 0 x 1 = 1 F = x 3 x 2 F = x 3 x 2 = 0 x 2 = 1 F = 0 F = x 3 Inputs

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F = x 3 (x 1 + x 2 x 0 ) x 0 = 0 x 0 = 1 F = x 3 x 1 F = x 3 (x 1 + x 2 ) x 1 = 0 x 1 = 1 F = 0 F = x 3 x 1 = 0 x 1 = 1 F = x 3 x 2 F = x 3 x 2 = 0 x 2 = 1 F = 0 F = x 3 MUX Select Lines

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x 1 = 0 x 0 = 0 x 0 = 1 F = x 3 x 1 F = x 3 (x 1 + x 2 ) x 1 = 1 F = 0 F = x 3 x 1 = 0 x 1 = 1 F = x 3 x 2 F = x 3 x 2 = 0 x 2 = 1 F = 0 F = x 3 1 0 sel x3x1x3x1 x 3 (x 1 + x 2 ) x0x0 F

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x 1 = 0 x 0 = 0 x 0 = 1 F = x 3 x 1 F = x 3 (x 1 + x 2 ) x 1 = 1 F = 0 F = x 3 x 1 = 0 x 1 = 1 F = x 3 x 2 F = x 3 x 2 = 0 x 2 = 1 F = 0 F = x 3 x3x1x3x1 1 0 sel x 3 (x 1 + x 2 ) 1 0 sel x0x0 x1x1 0 x3x3 The branch for x 0 = 0 F

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x 1 = 0 x 0 = 0 x 0 = 1 F = x 3 x 1 F = x 3 (x 1 + x 2 ) x 1 = 1 F = 0 F = x 3 x 1 = 0 x 1 = 1 F = x 3 x 2 F = x 3 x 2 = 0 x 2 = 1 F = 0 F = x 3 x3x1x3x1 1 0 sel x 3 (x 1 + x 2 ) 1 0 sel x0x0 x1x1 0 x3x3 1 0 x1x1 x3x2x3x2 x3x3 The branch for x 0 = 1 F

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x 1 = 0 x 0 = 0 x 0 = 1 F = x 3 x 1 F = x 3 (x 1 + x 2 ) x 1 = 1 F = 0 F = x 3 x 1 = 0 x 1 = 1 F = x 3 x 2 F = x 3 x 2 = 0 x 2 = 1 F = 0 F = x 3 x3x1x3x1 1 0 sel x 3 (x 1 + x 2 ) 1 0 sel x0x0 x1x1 0 x3x3 1 0 x1x1 x3x2x3x2 x3x3 The branch for x 1 = 0 1 0 sel x2x2 x3x3 0 F

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F = x 3 (x 1 + x 2 x 0 ) Starting with x 0 Shannon’s Decomposition 4 Multiplexers 1 0 sel 1 0 x0x0 x1x1 0 x3x3 1 0 x1x1 x3x3 1 0 x2x2 x3x3 0 F

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F = x 3 (x 1 + x 2 x 0 ) Starting with x 1 Shannon’s Decomposition 3 Multiplexers 1 0 sel 1 0 x1x1 x0x0 0 1 0 x2x2 x3x3 F x3x3 0

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16-input tree multiplexer

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Lecture #28 Page 1 ECE 4110– Sequential Logic Design Lecture #28 Agenda 1.Counters Announcements 1.HW #13 assigned 2.Next: Test #2 Review.

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