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ECE2030 Introduction to Computer Engineering Lecture 14: Sequential Logic Circuits Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering.

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Presentation on theme: "ECE2030 Introduction to Computer Engineering Lecture 14: Sequential Logic Circuits Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering."— Presentation transcript:

1 ECE2030 Introduction to Computer Engineering Lecture 14: Sequential Logic Circuits Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering Georgia Tech

2 2 Sequential Logic Circuits Sequential circuits –Combinational logic circuits –State information (stored in memory) Output is a function of inputs and present state Can be synchronous or asynchronous Combinational circuits inputs outputs Storage Element delay PresentStateNextState Controller by a periodic clock or an event trigger

3 3 State machine example A TV channel control CH 2 CH 3 CH

4 4 Sequential Logic Circuits Synchronous Circuits use clock pulse to synchronize For a typical synchronous design, data are latched into the storage upon clock transition (edge-triggered) Combinational circuits inputs outputs Storage Element PresentStateNextState clock

5 5 Closed-Loop Logic for Storing Information 1 0 A buffer Tpd

6 6 SR Latch S R Q QNQNQNQN

7 7 SRQQNQN 00QQ S Q QNQNQNQN R Reset Set Undefined No Change

8 8 SR Latch SRQQNQN QQ R Q QNQNQNQN S Reset Set Undefined No Change

9 9 SR Latch w/ Control CSRQQNQN 0XXQQ 100QQ Q QNQNQNQN R C S Reset Set Undefined No Change

10 10 Issue of an SR Latch or SR Latch S Q QNQNQNQN R S R SRQQNQN 00QQ Q QNQNQNQN Race, and Unstable

11 11 D Latch Q QNQNQNQN C D CDQQNQN 0XQQ

12 12 D Latch  Keeping Data for Read QQ

13 13 D D Latch  Writing Data D D QQ

14 14 10T D Latch w/ Transmission Gates D En En En QQ

15 15 10T D Latch w/ Transmission Gates D En=1 En QQD Writing DataD DEn

16 16 10T D Latch w/ Transmission Gates D_new En=0 En QQ Writing DataD DD En

17 17 D Latch Symbol D En QQ EnDQQ 0XNC NC: No Change

18 18 Latch is Transparent D Latch is called “transparent” or “level sensitive” Output follows input instantaneously En D QQ Transparent

19 19 Transparency Property D En Q Transparent Latch D En Q Storage Cell 0 D En Q Storage Cell 1 Latch acts like a Wire

20 20 Problem of Transparency A momentary input change tunnels through the latch and the entire circuitry What problem this can cause? D En Q TransparentLatch Other Logic Circuits

21 21 Problem of Transparency En TransparentLatch 1 DQD

22 22 Eliminating Transparency Separating the input and output, so they are independently controlled Only open one gate at a time to avoid tunneling En TransparentLatch DQ En TransparentLatch DQ

23 23 Behavior of Master-Slave Latches En DQ En DQ 1 0 Storage Cell Storage 0 Cell (0) En DQ En DQ 0 1 Storage 1 Cell (1) Storage Cell

24 24 Behavior of Master-Slave Latches En D1Q1 En D2Q2 En D1 (initialized to1) D1 Q1=D2 Q2 A Toggle Cell, will discuss more later

25 25 Behavior of Master-Slave Latches En D1Q1 En D2Q2 En D1(input) Q1=D2 Q2

26 26 Behavior of Master-Slave Latches En D1Q1 En D2Q2 En Q1=D2 Q2 D1(input)

27 27 Flip-Flop (F/F) D1Q1D2Q2 Enable (or clock) InputOutput Enable (or clock) InputOutput 1-bit Flip Flop

28 28 Negative Edge Triggered Flip-Flop D1Q1D2Q2 clock Input Q1=D2 Output Enable (or clock) InputOutput

29 29 Positive Edge Triggered Flip-Flop D1Q1D2Q2 clock Q1=D2 Enable (or clock) InputOutput Input Output

30 30 Positive Edge Triggered Flip-Flop D1Q1D2Q2 clock Q1=D2 Enable (or clock) InputOutput Input Output

31 31 Flip Flops Symbols D C Q Q D C Q Q Positive Edge Triggered D Flip Flop Negative Edge Triggered D Flip Flop

32 32 Dual-phase Non-overlapped Clocks In reality, enable control is not ideal Use dual phase clocks (  1 and  2) to replace Enable and its inversion 1111Q1=D2 Input Output 2222 D2 follows  1 while Output follows  2

33 33 Dual-Phase Non-overlapped Clocks D1Q1D2Q2 InputOutput InputOutput 1-bit Flip Flop 1111 2222 1111 2222


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