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Shift Registers Module M11.1 Section 7.3. 4-Bit Shift Register.

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Presentation on theme: "Shift Registers Module M11.1 Section 7.3. 4-Bit Shift Register."— Presentation transcript:

1 Shift Registers Module M11.1 Section 7.3

2 4-Bit Shift Register

3 shift4.abl MODULE Shift4 TITLE '4-bit Shift Register A. Student, 7/22/02' DECLARATIONS " INPUT PINS " PB PIN 10; " push-button switch (clock) Clear PIN 7; " Switch 2 Load PIN 11; " Switch 3 data_in PIN 70; " Switch 8 " OUTPUT PINS " Q3..Q0 PIN 39,37,36,35 ISTYPE 'reg buffer'; " LED 5..8 Q = [Q3..Q0]; " 3-bit output vector

4 shift4.abl (cont’d) EQUATIONS Q.c = PB; Q0.d = !Clear & data_in; Q1.d = !Clear & Q0; Q2.d = !Clear & Q1; Q3.d = !Clear & Q2; END Shift4

5 4shift.si CUPL Simulation File

6 4shift.si CUPL Simulation File

7 CUPL Simulation Output File

8 Ring Counter

9 ring4.abl MODULE Ring4 TITLE '4-bit Ring Counter A. Student, 7/22/02' DECLARATIONS " INPUT PINS " PB PIN 10; " push-button switch (clock) Clear PIN 7; " Switch 2 " OUTPUT PINS " Q3..Q0 PIN 39,37,36,35 ISTYPE 'reg buffer'; " LED 5..8 Q = [Q3..Q0]; " 3-bit output vector

10 ring4.abl (cont’d) EQUATIONS Q.c = PB; Q0.d = !Clear & Q3; Q1.d = !Clear & Q0; Q2.d = !Clear & Q1; Q3.d = !Clear & Q2 # Clear; END Ring4

11 ring4.si CUPL Simulation File

12 ring4.si CUPL Simulation File

13 CUPL Simulation Output File

14 Ring Counter

15 Johnson Counter

16 Exercise Detect input sequence 1101 fsm din dout clk clr din dout

17 Use Shift Register CLK DQ !QCLK DQ !QCLK DQ !QCLK DQ !Q CLK Q0Q1Q2Q dout din

18 Lab 8 Johnson Counter & Random Number Generator CLK DQ !QCLK DQ !QCLK DQ !QCLK DQ !Q CLK Q3Q2Q1Q0 Random Number Generator

19 Q3 Q2 Q1 Q C E F B Q3 Q2 Q1 Q A D


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