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Pulse-Width Modulated DACLecture 11.3 Verilog Section 11.5
module counter8 ( Q ,clr ,clk );input clr ; wire clr ; input clk ; wire clk ; output [7:0] Q ; reg [7:0] Q ; // 8-bit counter clk or posedge clr) begin if(clr == 1) Q <= 0; else Q <= Q + 1; end endmodule
module PWM(clk,clr,duty,pwm);input clk, clr; input [7:0] duty; output pwm; reg pwm; wire [7:0] count; wire set, reset; assign set = &count; assign reset = (count == duty); set or posedge reset or posedge clr) begin if(clr == 1) pwm <= 0; else if(set == 1) pwm <= 1; if(reset == 1) end counter8 CNT(.Q(count),.clr(clr),.clk(clk));
Simulation of PWM
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